Reversible top/bottom MEMS package

• US 8,981,537 B2
• Filed: 01/11/2012
• Issued: 03/17/2015
• Est. Priority Date: 03/04/2009
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Bolognia, David, Kuo, Bob Shih-Wei, Troche, Bud
• Primary Examiner(s): Luu, Chuong A
• Application Number:
  US13/348,304
• Publication Number:
  US 20120104629A1
• Time in Patent Office: 1,161 Days
• Field of Search: 257/660, 257/433, 257/680, 257/659, 257/774, 257/648, 257/685, 257/687, 257/699, 257/700
• US Class Current: 257/660
• CPC Class Codes: B81B 2201/0257 Microphones or microspeakers
• CPC Class Codes: B81B 2207/012 the micromechanical device and the control or processing electronics being separate parts in the same package
• CPC Class Codes: B81B 2207/095 through the lid
• CPC Class Codes: B81B 7/0061 suitable for fluid transfer from the MEMS out of the package or vice versa, e.g. transfer of liquid, gas, sound
• CPC Class Codes: B81B 7/0064 for protecting against electromagnetic or electrostatic interferences
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48095 Kinked
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/165 : Containers
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor device has a base substrate having a plurality of metal traces and a plurality of base vias. An opening is formed through the base substrate. At least one die is attached to the first surface of the substrate and positioned over the opening. A cover substrate has a plurality of metal traces. A cavity in the cover substrate forms side wall sections around the cavity. The cover substrate is attached to the base substrate so the at least one die is positioned in the interior of the cavity. Ground planes in the base substrate are coupled to ground planes in the cover substrate to form an RF shield around the at least one die.

Claims

1. A semiconductor device comprising:

a base substrate having a plurality of metal traces;

an opening formed through the base substrate;

at least one die attached to the first surface of the substrate and positioned over the opening; and

a cover substrate, a cavity in the cover substrate forming side wall sections around the cavity, the cover substrate attached to the base substrate wherein the at least one die is positioned in the interior of the cavity; and

ground vias formed in the cover substrate to ground the base substrate to the cover substrate, wherein the ground vias are exposed.

2. A semiconductor device in accordance with claim 1, wherein at least one of the ground vias is formed in the side wall sections to couple a ground planes in the base substrate to a ground plane in the cover substrate.

3. A semiconductor device in accordance with claim 1, wherein a side sections of at least one of the ground vias is exposed.

4. A semiconductor device in accordance with claim 1, further comprising signal vias formed in the side wall sections and coupled to metal traces in the base substrate and cover substrate.

5. A semiconductor device in accordance with claim 4, wherein the signal vias are formed along an inner perimeter of the side wall members and the conductive ground vias are formed along an outer perimeter of the side wall members.

6. A semiconductor device in accordance with claim 1, further comprising a plurality of wires, wherein each wire has a first end attached to a ground plane on the base substrate and a second end attached to the ground plane on the base substrate, each of the wires forming a loop wherein a top section of each loop contacts a ground plane of the cover substrate.

7. A semiconductor device in accordance with claim 1, further comprising a plurality of cover vias formed in the cover substrate, wherein at least one of the cover vias is connected to a plurality of pads when the cover substrate is attached to an I/O board.

8. A semiconductor device comprising:

a base substrate;

an opening formed through the base substrate;

a first electronic component attached to the first surface of the base substrate and positioned over the opening;

a second electronic component attached to the first surface of the base substrate next to the first electronic component;

a first set of wirebonds to couple the first electronic component to the second electronic component;

a cover substrate having a cavity in the cover substrate forming side wall sections around the cavity, the cover substrate attached to the base substrate wherein the first and second electronic components are positioned in the interior of the cavity; and

ground vias formed in the cover substrate to ground the base substrate to the cover substrate, wherein the ground vias are exposed.

9. A semiconductor device in accordance with claim 8, wherein the ground vias are formed in the side wall sections to couple a ground plane in the base substrate to a ground plane in the cover substrate.

10. A semiconductor device in accordance with claim 8, wherein a side section at least one of the ground vias is exposed.

11. A semiconductor device in accordance with claim 8, further comprising signal vias formed in the side wall sections and coupled to metal traces in the base substrate and cover substrate.

12. A semiconductor device in accordance with claim 11, wherein the signal vias are formed along an inner perimeter of the side wall members and the conductive ground vias are formed along an outer perimeter of the side wall members.

13. A semiconductor device in accordance with claim 8, further comprising a plurality of wires, wherein each wire has a first end attached to a ground plane on the base substrate and a second end attached to the ground plane on the base substrate, each of the wires forming a loop wherein a top section of each loop contacts a ground plane of the cover substrate.

14. A semiconductor device in accordance with claim 8, further comprising a plurality of cover vias formed in the cover substrate, wherein at least one of the cover vias is connected to a plurality of pads when the cover substrate is attached to an I/O board.

15. A semiconductor device comprising:

a base substrate having a plurality of metal traces;

an opening formed through the base substrate;

at least one die attached to the first surface of the substrate and positioned over the opening; and

a cover substrate, a cavity in the cover substrate forming side wall sections around the cavity, the cover substrate attached to the base substrate wherein the at least one die is positioned in the interior of the cavity; and

means formed in the cover substrate for grounding the base substrate to the cover substrate, wherein the means are exposed.

16. A semiconductor device in accordance with claim 15, further comprising means coupled to metal traces on the base substrate and cover substrate for forming I/O pathways between the base substrate and cover substrate.

17. A semiconductor device in accordance with claim 16, wherein the means for forming I/O pathways are formed along an inner perimeter of the side wall members and the means for grounding are formed along an outer perimeter of the side wall members.

18. A semiconductor device in accordance with claim 15, further comprising a plurality of wires, wherein each wire has a first end attached to a ground plane on the base substrate and a second end attached to the ground plane on the base substrate, each of the wires forming a loop wherein a top section of each loop contacts a ground plane of the cover substrate.

19. A semiconductor device in accordance with claim 15, further comprising a plurality of cover vias formed in the cover substrate, wherein at least one of the cover vias is connected to a plurality of pads when the cover substrate is attached to an I/O board.

20. A semiconductor device in accordance with claim 16, wherein the means for forming I/O pathways are signal vias formed along an inner perimeter of the side wall members and the means for grounding are grounding vias formed along an outer perimeter of the side wall members.