3-D IC device with enhanced contact area

• US 8,981,567 B2
• Filed: 07/23/2013
• Issued: 03/17/2015
• Est. Priority Date: 03/13/2013
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Hu, Chih-Wei, Yeh, Teng-Hao
• Primary Examiner(s): Gumedzoe, Peniel M
• Application Number:
  US13/948,508
• Publication Number:
  US 20140264898A1
• Time in Patent Office: 602 Days
• Field of Search: 257/315, 257/773, 438/622
• US Class Current: 257/773
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A device includes a substrate with a recess, having a bottom and sides, extending into the substrate from the substrate'"'"'s upper surface. The sides include first and second sides oriented transversely to one another. A stack of alternating active and insulating layers overlie the substrate'"'"'s surface and the recess. At least some of the active layers have an upper and lower portions extending along upper and lower planes over and generally parallel to the upper surface and to the bottom, respectively. The active layers have first and second upward extensions positioned along the first and second sides to extend from the lower portions of their respective active layers. Conductive strips adjoin the second upward extensions of the said active layers. The conductive strips can comprise sidewall spacers on the sides of the second upward extensions, the conductive strips connected to overlying conductors by interlayer conductors.

Claims

1. A device comprising:

a substrate comprising an upper surface and a recess extending into the substrate from the upper surface;

the recess having a bottom and sides extending between the upper surface and the bottom, the sides comprising first and second sides oriented transversely to one another;

a stack of alternating active and insulating layers overlying the upper surface of the substrate and the recess;

each of a plurality of said active layers having an upper portion extending along an upper plane over and generally parallel to the upper surface and a lower portion extending along a lower plane over and generally parallel to the bottom;

each of the plurality of said active layers comprising first and second upward extensions positioned along the first and second sides and extending from the lower portions of their respective active layers; and

a plurality of conductive strips adjoining the second upward extensions of the plurality of said active layers.

2. The device of claim 1, wherein the plurality of conductive strips comprise sidewall spacers on sides of the second upward extensions.

3. The device of claim 1, wherein the second upward extensions are oriented generally perpendicular to the upper surface and the first upward extensions are downwardly and inwardly sloped at an acute angle to the upper surface.

4. The device of claim 1, wherein:

the recess is a generally rectangular recess with a third side opposite the first side and a fourth side opposite the second side; and

the second and fourth sides are oriented generally perpendicular to the upper surface and the first and third side are downwardly and inwardly sloped oriented at acute angles to the upper surface.

5. The device of claim 1, wherein the upper and lower planes are generally parallel to one another.

6. The device of claim 1, wherein the conductive strips have lower and upper ends, the lower ends being in the recess, the upper ends being configured to connect to overlying conductors by interlayer conductors.

7. The device of claim 6, wherein the upper ends of at least some of the conductive strips are at the same level, the same level being parallel to the upper surface.

8. The device of claim 6, wherein the upper ends are at different levels relative to the upper surface.

9. The device of claim 6, wherein the upper ends of the conductive strips provide landing areas for the interlayer conductors.

10. The device of claim 6, wherein the upper ends of the conductive strips and adjacent ones of the second upward extensions provide landing areas for the interlayer conductors.

11. The device of claim 1, wherein the first upward extensions connect the upper and lower portions of their respective active layers.

12. The device of claim 1, wherein:

the upper surface comprises an array area adjacent to the recess; and

the stack of alternating active and insulating layers comprises elements of a memory array at the array area.

13. A method for forming electrical connections with active layers of a stack of alternating active and insulating layers of a device, the method comprising:

forming a recess in a substrate, the substrate comprising an upper surface with the recess extending into the substrate from the upper surface, the recess having a bottom and sides extending between the upper surface and the bottom, the sides comprising first and second sides oriented transversely to one another;

forming a stack of alternating active and insulating layers over the upper surface of the substrate and the recess;

the stack forming step comprising;

forming an upper portion of each of a plurality of the active layers to be along an upper plane and over and generally parallel to the upper surface; and

forming a lower portion of each of the plurality of active layers to be along a lower plane and over and generally parallel to the bottom; and

forming first and second upward extensions of each of the plurality of active layers to be positioned along the first and second sides and to extend from the lower portions of their respective active layers; and

during the stack forming step, forming conductive strips adjoining the second upward extensions of the plurality of active layers.

14. The method of claim 13, wherein the recess forming step comprises forming the first side as a downwardly and inwardly sloped first side oriented at an acute angle to the upper surface.

15. The method of claim 14, wherein:

the recess forming step comprises forming the second side oriented generally perpendicular to the upper surface;

the conductive strips forming step comprising depositing a layer of conductive material along the bottom and sides of the recess, and anisotropically etching the conductive material; and

selecting the acute angle of the sloped first side so that the conductive material is removed from along the bottom and the first side during the anisotropically etching of the conductive material while leaving conductive material along the second side thereby forming a conductive strip.

16. The method of claim 14, wherein:

the recess forming step comprises forming a generally rectangular recess having first, second, third and fourth sides with the first and third sides being opposite one another and being downwardly and inwardly sloped sides oriented at acute angles to the upper surface; and

the conductive strips forming step comprises forming the conductive strips as sidewall spacers at the second and fourth sides but not at the first or third sides.

17. The method of claim 13, wherein:

the conductive strips forming step comprises forming the conductive strips as sidewall spacers on sides of the second upward extensions but not on sides of the first upward extensions.

18. The method of claim 13, further comprising forming interlayer conductors contacting upper surfaces of the conductive strips, the upper surfaces defining landing areas for the interlayer conductors.

19. The method of claim 18, wherein the landing areas extend along a landing area plane generally parallel to the upper surface or at an acute angle to the upper surface.

20. The method of claim 13, further comprising forming interlayer conductors contacting landing areas created by the upper ends of the conductive strips and adjacent ones of the second upward extensions.