Simulated wirebond semiconductor package

• US 8,981,568 B2
• Filed: 06/07/2010
• Issued: 03/17/2015
• Est. Priority Date: 06/16/2009
• Status: Active Grant

• Current Assignee: HSIO Technologies LLC
• Original Assignee: HSIO Technologies LLC
• Inventors: Rathburn, James
• Primary Examiner(s): Smoot, Stephen W
• Assistant Examiner(s): Chin, Edward
• Application Number:
  US13/319,120
• Publication Number:
  US 20120061851A1
• Time in Patent Office: 1,744 Days
• Field of Search: 257/E21.511, 257/E23.066, 257/E23.178, 257/774, 257/E21.502, 438/215
• US Class Current: 257/774
• CPC Class Codes: B23K 1/0016 Brazing of electronic components
• CPC Class Codes: B23K 20/004 Wire welding
• CPC Class Codes: B23K 2101/42 Printed circuits
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/50 Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto thin flexible metallic tape with or without a film carrier H01L23/49572, flexible insulating substrates H01L23/4985, H01L23/5387
• CPC Class Codes: H01L 24/86 using tape automated bonding [TAB]
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor package with simulated wirebonds. A substrate is provided with a plurality of first pads on a first surface and a plurality of second pads on a second surface. Each of the first pads are electrically coupled to one or more of the second pads. At least one semiconductor device is located proximate the first surface of a substrate. The simulated wirebonds include at least a first dielectric layer selectively printed to create a plurality of recesses, and a conductive material located in the recesses to form first and second contact pads, and electrical traces electrically coupling the first and second contact pads. The first contact pads are electrically coupled to terminals on the semiconductor device and the second contact pads are electrically coupled to the first pads on the first surface of the substrate. An overmolding material seals the semiconductor device and the simulated wirebonds.

Claims

1. A semiconductor package comprising:

a substrate comprising a plurality of first pads on a first surface and a plurality of second pads on a second surface, each of the first pads electrically coupled to one or more of the second pads;

at least one semiconductor device comprising a first surface located proximate the first surface of a substrate and a second surface with terminals oriented to face away from the first surface of the substrate;

at least one simulated wirebond comprising at least a first dielectric layer selectively printed to create a plurality of recesses, and a conductive material located in the recesses to form first wirebond contact pads and second wirebond contact pads, and conductive traces electrically coupling the first and second wirebond contact pads, the conductive traces formed in the recesses comprise a generally rectangular cross-sectional shape, the first wirebond contact pads electrically coupled to the terminals on the semiconductor device and the second wirebond contact pads electrically coupled to the first pads on the first surface of the substrate so the simulated wirebond extends from the first surface of the substrate to the second surface of the semiconductor device; and

overmolding material sealing the semiconductor device and the simulated wirebonds to the first surface of the substrate.

2. The semiconductor package of claim 1 wherein the at least first dielectric layer comprises a plurality of dielectric layers substantially surrounding the conductive traces.

3. The semiconductor package of claim 1 wherein the conductive traces comprise a circuit geometry that extends beyond electrically coupling the first and second wirebond contact pads.

4. The semiconductor package of claim 1 wherein conductive traces comprise substantially rectangular cross-sectional shapes.

5. The semiconductor package of claim 1 wherein the conductive traces comprises a conductive plating deposited in a plurality of the recesses.

6. The semiconductor package of claim 1 comprising a compliant material located between the second wirebond contact pads on the simulated wirebond and the overmolding material.

7. The semiconductor package of claim 1 comprising at least one electrical device printed on one of the dielectric layers and electrically coupled to at least one of the conductive traces.

8. The semiconductor package of claim 1 comprising:

a plurality of semiconductor devices located proximate the first surface of the substrate; and

circuit geometry printed in dielectric layers electrically coupling terminals on at least two semiconductor devices.

9. The semiconductor package of claim 1 comprising:

a plurality of semiconductor devices located proximate the first surface of the substrate; and

a plurality of simulated wirebonds electrically coupling terminals on the semiconductor devices to pads on the first surface of the substrate.

10. The semiconductor package of claim 1 comprising:

a plurality of semiconductor devices arranged in a stacked configuration proximate the first surface of the substrate; and

a plurality of simulated wirebonds electrically coupling terminals on the semiconductor devices to pads on the first surface of the substrate.

11. The semiconductor package of claim 1 wherein the conductive traces comprise a stacked configuration with tiered or staggered first wirebond contact pads.

12. The semiconductor package of claim 1 wherein the simulated wirebond includes one or more of optical fibers, printed optical material, coaxial conductors, radio-frequency circuits, shielding, or antennae.

13. An electrical assembly comprising:

the semiconductor package of claim 1; and

a circuit member with a plurality of contact pads electrically coupled to the pads on the second surface of the substrate.

14. The semiconductor package of claim 1 wherein the simulated wirebond extends beyond the semiconductor package.

15. The semiconductor package of claim 1 wherein the simulated wirebond extends beyond the terminals on the semiconductor device and the conductive traces are accessible from outside the semiconductor package.

16. The semiconductor package of claim 1 comprising optical material located in a plurality of recesses in the simulated wirebond, wherein the first wirebond contact pads optically couple to terminals on the semiconductor device and second wirebond contact pads optically couple to the substrate.

17. The semiconductor package of claim 1 wherein at least the first dielectric layer comprises a flexible material.

18. The semiconductor package of claim 1 wherein the first surface of the semiconductor device is adjacent the first surface of the substrate.

19. The semiconductor package of claim 1 wherein the second surface of the semiconductor device is generally parallel to, and offset from, the first surface of the substrate.

20. The semiconductor package of claim 1 wherein a portion of the simulated wirebond that extends from the first surface of the substrate to the second surface of the semiconductor device is unattached to either the substrate or the semiconductor device.