Method and apparatus for bypass mode low dropout (LDO) regulator

• US 8,981,745 B2
• Filed: 03/07/2013
• Issued: 03/17/2015
• Est. Priority Date: 11/18/2012
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Price, Burt L., Shah, Dhaval R., Kolla, Yeshwant Nagaraj
• Primary Examiner(s): Berhane, Adolf
• Assistant Examiner(s): NASH, GARY A
• Application Number:
  US13/788,546
• Publication Number:
  US 20140139197A1
• Time in Patent Office: 740 Days
• Field of Search: 323/273, 323/274, 323/282, 323/284, 323/289, 323/350, 323/351, 361/8, 361/13, 361/18, 361 54- 57
• US Class Current: 323/274
• CPC Class Codes: G05F 1/46 wherein the variable actually regulated by the final control device is dc G05F1/625 takes precedence
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence

Abstract

A bypass low dropout regulator has a pass gate coupled to a voltage rail. The pass gate receives a pass gate control signal on a pass gate control line and controllably drops a voltage from a rail to a regulated output in accordance with the pass gate control signal. A differential amplifier generates the pass gate control voltage using a reference and feedback from the regulated output. A bypass switch selectively bypasses the regulator control signal, in response to a bypass signal, by placing a pass gate ON voltage on the pass gate control line. Optionally, and ON-OFF mode circuit selectively disables the pass gate in response to a system ON-OFF signal.

Claims

1. A bypass low dropout regulator comprising:

a pass gate coupled to a supply rail and having a regulator output and a control terminal, configured to controllably couple, in response to receiving a pass gate control signal on the control terminal, the supply rail to the regulator output;

a differential amplifier, configured to generate the pass gate control signal, based on a reference voltage and a feedback of the regulator output;

a pass gate control line, coupling an output of the differential amplifier to the control terminal, for carrying the pass gate control signal; and

a bypass mode circuit configured to selectively ON override the pass gate control signal in response to a bypass mode signal, wherein the ON override places a pass gate ON hard voltage on the control terminal,

wherein the bypass mode circuit is configured to receive the bypass mode signal at a value switchable between a bypass mode ON signal and a bypass mode OFF signal, and is configured to ON override the pass gate control signal in response to receiving the bypass mode ON signal, and

wherein the bypass mode circuit is configured to perform the ON override by shorting the pass gate control line, in response to receiving the bypass mode ON signal, to a power rail having the pass gate ON hard voltage.

2. The bypass low dropout regulator of claim 1, wherein the bypass mode circuit comprises a bypass mode switch configured to receive the bypass mode signal and, in response to the bypass mode ON signal, to perform the shorting and, in response to the bypass mode OFF signal, to not perform the shorting.

3. A bypass low dropout regulator comprising:

a pass gate coupled to a supply rail and having a regulator output and a control terminal, configured to controllably couple, in response to receiving a pass gate control signal on the control terminal, the supply rail to the regulator output;

a differential amplifier, configured to generate the pass gate control signal, based on a reference voltage and a feedback of the regulator output;

a bypass mode circuit configured to selectively ON override the pass gate control signal in response to a bypass mode signal, wherein the bypass mode circuit is configured to receive the bypass mode signal at a value switchable between a bypass mode ON signal and a bypass mode OFF signal, and is configured to ON override the pass gate control signal in response to receiving the bypass mode ON signal, wherein the ON override places a pass gate ON hard voltage on the control terminal;

an ON-OFF mode switch configured to OFF override the pass gate control signal in response to receiving an LDO disable signal, wherein the OFF override places a pass gate OFF voltage on the control terminal; and

an ON-OFF/bypass resolution logic, wherein the ON-OFF/bypass resolution logic is configured to receive the bypass mode signal and a system ON-OFF mode signal and, in response, to select in accordance with a given priority between generating the LDO disable signal and not generating the LDO disable signal.

4. The bypass low dropout regulator of claim 3, wherein the ON-OFF/ bypass resolution logic is further configured to generate the LDO disable signal in response to a concurrence of receiving the bypass mode OFF signal and the system ON-OFF mode OFF signal.

5. The bypass low dropout regulator of claim 3, wherein the differential amplifier comprises:

a first branch having a first transistor;

a second branch having a second transistor, wherein the first branch and the second branch are coupled at a common node; and

a switchable tail current source coupled to the common node and controlled by the system ON-OFF mode signal, configured to switch to an ON state and source an operating biasing current in response to the system ON-OFF mode ON signal, and to switch to an OFF state and source an OFF state biasing current, less than the operating biasing current, in response to the system ON-OFF mode OFF signal.

6. A bypass low dropout regulator, comprising:

a pass gate coupled to a supply rail and having a regulator output and a control terminal, configured to controllably couple, in response to receiving a pass gate control signal on the control terminal, the supply rail to the regulator output;

a differential amplifier, configured to generate the pass gate control signal, based on a reference voltage and a feedback of the regulator output;

a bypass mode circuit configured to selectively ON override the pass gate control signal in response to a bypass mode signal, wherein the ON override places a pass gate ON hard voltage on the control terminal;

an ON/OFF bypass resolution logic configured to receive the bypass mode signal and a system ON-OFF mode signal and, in response to a concurrence of receiving the bypass mode OFF signal and the system ON-OFF mode OFF signal, to generate an LDO disable signal; and

an ON-OFF mode switch configured to receive the LDO disable signal and, in response, perform an OFF override of the pass gate control signal, wherein the OFF override places a pass gate OFF voltage on the control terminal.

7. The bypass low dropout regulator of claim 6, wherein the differential amplifier comprises:

a first branch having a first transistor;

a second branch having a second transistor, wherein the first branch and the second branch are coupled at a common node; and

a switchable tail current source coupled to the common node and controlled by the system ON-OFF mode signal.

8. The bypass low dropout regulator of claim 6, wherein the a switchable tail current source is configured to switch to an ON state and source an operating biasing current in response to the system ON-OFF mode ON signal, and to switch to an OFF state and source an OFF state biasing current, less than the operating biasing current, in response to the system ON-OFF mode OFF signal.

9. A method for bypassing a low dropout regulator comprising:

generating a pass gate control signal based on a difference between a regulated output voltage of a pass gate and a reference voltage;

receiving a bypass mode signal that is switchable between a bypass mode ON signal and a bypass mode OFF signal;

receiving a system ON-OFF mode signal that is switchable between a system ON-OFF mode ON signal and a system ON-OFF mode OFF signal; and

conditionally controlling a conductance of the pass gate based at least on the pass gate control signal, receiving the system ON-OFF mode signal, and receiving the bypass mode signal, wherein the conductance of the pass gate is based, at least in part, on the pass gate control signal when receiving the bypass mode OFF signal,

wherein, when receiving the bypass mode ON signal, the conductance of the pass gate is based, at least in part, on the bypass mode ON signal, and

wherein conditionally controlling the conductance includes, in response to a concurrence of receiving the bypass mode OFF signal and the system ON-OFF mode OFF signal, disabling the pass gate.

10. The method of claim 9, wherein controlling the conductance of the pass gate when receiving the bypass mode ON signal comprises placing a pass gate ON voltage on a control terminal of the pass gate.

11. The method of claim 9, wherein controlling the conductance of the pass gate when receiving the bypass mode ON signal comprises shorting a control terminal of the pass gate to a power rail having a pass gate ON voltage.

12. The method of claim 9, wherein controlling the conductance of the pass gate when receiving the bypass mode ON signal comprises overriding the pass gate control signal.

13. The method of claim 9, wherein conditionally controlling the conductance of the pass gate further includes, in response to a concurrence of receiving the bypass mode ON signal and the system ON-OFF mode ON signal, switching the pass gate ON hard.

14. The method of claim 9, wherein disabling the pass gate comprises placing a pass gate OFF voltage on a control terminal of the pass gate.

15. An apparatus for bypassing a low dropout regulator comprising:

means for generating a pass gate control signal based on a difference between a regulated output voltage of a pass gate and a reference voltage; and

means for conditionally controlling a conductance of the pass gate based at least on the pass gate control signal and receiving a bypass mode signal that is switchable between a bypass mode ON signal and a bypass mode OFF signal,

wherein the means for conditionally controlling is configured to control the conductance of the pass gate based, at least in part, on the pass gate control signal when receiving the bypass mode OFF signal and, when receiving the bypass mode ON signal, to control the conductance of the pass gate based, at least in part, on the bypass mode ON signal, and

wherein the means for conditionally controlling the conductance of the pass gate is further configured to control the conductance of the pass gate further based on receiving a system ON-OFF mode signal that is switchable between a system ON-OFF mode ON signal and a system ON-OFF mode OFF signal, and to include in the controlling, in response to a concurrence of receiving the bypass mode OFF signal and the system ON-OFF mode OFF signal, disabling the pass gate.

16. The apparatus of claim 15, wherein the means for conditionally controlling the conductance of the pass gate is further configured to control the conductance of the pass gate, in response to a concurrence of receiving the bypass mode ON signal and the system ON-OFF mode OFF signal, switching the pass gate ON hard.