Compliant printed circuit semiconductor tester interface

• US 8,981,809 B2
• Filed: 06/28/2010
• Issued: 03/17/2015
• Est. Priority Date: 06/29/2009
• Status: Active Grant

• Current Assignee: HSIO Technologies LLC
• Original Assignee: HSIO Technologies LLC
• Inventors: Rathburn, James
• Primary Examiner(s): Baldridge, Benjamin M
• Application Number:
  US13/319,203
• Publication Number:
  US 20120056640A1
• Time in Patent Office: 1,723 Days
• Field of Search: 324/762.03
• US Class Current: 324/762.03
• CPC Class Codes: G01R 1/0466 concerning contact pieces or mechanical details, e.g. hinges or cams; Shielding
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 1/0735 arranged on a flexible frame or film
• CPC Class Codes: G01R 1/07378 using an intermediate adapter, e.g. space transformers G01R1/07371 takes precedence
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base

Abstract

A compliant printed circuit semiconductor tester interface that provides a temporary interconnect between terminals on integrated circuit (IC) devices being tested. The compliant printed circuit semiconductor tester interface includes at least one dielectric layer printed with recesses corresponding to a target circuit geometry. A conductive material is deposited in at least a portion of the recesses comprising a circuit geometry and a plurality of first contact pads accessible along a first surface of the compliant printed circuit. At least one dielectric covering layer is preferably applied over the circuit geometry. A plurality of openings in the dielectric covering layer are provided to permit electrical coupling of terminals on the IC device and the first contact pads. Testing electronics that to test electrical functions of the IC device are electrically coupled to the circuit geometry.

Claims

1. A compliant printed circuit semiconductor tester interface providing a temporary interconnect between terminals on integrated circuit (IC) devices being tested, the compliant printed circuit semiconductor tester interface comprising:

at least one dielectric layer printed with recesses corresponding to a target circuit geometry;

a conductive material deposited in at least a portion of the recesses comprising a circuit geometry and a plurality of first contact pads formed in the at least one dielectric layer, the circuit geometry comprising a plurality of conductive traces electrically coupled to the plurality of first contact pads accessible along a first surface of the compliant printed circuit;

at least one dielectric covering layer;

a plurality of openings in the dielectric covering layer permitting electrical coupling of the terminals on the IC device and the first contact pads, the circuit geometry extending beyond the openings in the covering layer;

one or more compliant layers positioned to elastically bias a plurality of the first contact pads against the terminals on the IC device; and

testing electronics electrically coupled to the portion of the circuit geometry that extends beyond the openings in the dielectric layer to test electrical functions of the IC device.

2. The compliant printed circuit semiconductor tester interface of claim 1 comprising at least one electrical device located on the compliant printed circuit and electrically coupled to the circuit geometry.

3. The compliant printed circuit semiconductor tester interface of claim 2 wherein the electrical devices comprise at least a portion of the testing electronics.

4. The compliant printed circuit semiconductor tester interface of claim 1 comprising at least one electrical device printed on one of the dielectric layers and electrically coupled to at least a portion of the circuit geometry.

5. The compliant printed circuit semiconductor tester interface of claim 4 wherein the electrical device is selected from one of shielding, near device decoupling, capacitors, transistors, resistors, filters, signal or power altering and enhancing devices, memory devices, embedded IC devices, or RF antennae.

6. The compliant printed circuit semiconductor tester interface of claim 1 comprising a socket housing coupled to the compliant printed circuit, the first contact pads positioned in a socket housing recess sized to receive the IC device.

7. The compliant printed circuit semiconductor tester interface of claim 1 comprising an optical quality material deposited in at least a portion of the recesses comprising one or more optical circuit geometries.

8. The compliant printed circuit semiconductor tester interface of claim 1 comprising one or more optical fibers located in at least a portion of the recesses comprising one or more optical circuit geometries.

9. The compliant printed circuit semiconductor tester interface of claim 1 comprising one or more of the first contact pads extend above the dielectric covering layer.

10. The compliant printed circuit semiconductor tester interface of claim 9 wherein the first contact pads comprise probe members of a probe assembly.

11. The compliant printed circuit semiconductor tester interface of claim 1 wherein the compliant printed circuit semiconductor tester interface is singulated adjacent at least one of the first contact pads.

12. The compliant printed circuit semiconductor tester interface of claim 1 wherein the conductive traces in the circuit geometry comprise substantially rectangular cross-sectional shapes.

13. The compliant printed circuit semiconductor tester interface of claim 1 wherein a conductive material, a non-conductive material, and a semi-conductive material are printed on a single layer.

14. The compliant printed circuit semiconductor tester interface of claim 1 comprising:

a first portion of the circuit geometry extending beyond the dielectric covering layer;

a compliant material located along a surface of the first portion of the circuit geometry; and

a second portion of the circuit geometry located on top of the compliant material, the first and second portions of the circuit geometry comprising an edge connector.

15. The compliant printed circuit semiconductor tester interface of claim 1 comprising at least one additional circuitry plane.

16. The compliant printed circuit semiconductor tester interface of claim 15 wherein the at least one additional circuitry plane comprises one of a ground plane, a power plane, an electrical connection to other circuit members, a dielectric layer, or a flexible circuit.

17. The compliant printed circuit semiconductor tester interface of claim 1 comprising a plurality of second contact pads accessible along a second surface of the compliant printed circuit, wherein the testing electronics are coupled to the circuit geometry through the second contact pads.