Level shifter with built-in logic function for reduced delay

• US 8,981,831 B1
• Filed: 09/11/2013
• Issued: 03/17/2015
• Est. Priority Date: 09/11/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kossel, Marcel A., Lim, Daihyun, Thiagarajan, Pradeep
• Primary Examiner(s): Hernandez, William
• Application Number:
  US14/024,233
• Publication Number:
  US 20150070069A1
• Time in Patent Office: 552 Days
• Field of Search: 327/333, 326/63, 326/68, 326/80, 326/81
• US Class Current: 327/333
• CPC Class Codes: H03K 19/018507 Interface arrangements

Abstract

A method and circuit for implementing a level shifter with built-in-logic function for reduced delay. The circuit including at least one set of inputs from a first power supply domain. The circuit further including at least two cross coupled field effect transistors (FETs) connected to a second power supply domain. The circuit further including a true logic gate connected to the first power supply domain and the at least two cross coupled FETs. The true logic gate being configured to generate a logic function based on the at least one set of inputs. The circuit further including a complementary logic gate connected to the first power supply domain and the at least two cross coupled FETs. The complementary logic gate being configured to generate a complement of the logic function based on the at least one set of inputs.

Claims

1. A circuit comprising:

at least one set of inputs from a first power supply domain;

at least two cross coupled field effect transistors (FETs) connected to a second power supply domain, wherein the at least two cross coupled FETs are pFETs;

a true logic gate connected to the first power supply domain and the at least two cross coupled FETs, wherein the true logic gate is comprised of at least one nFET and configured to generate a logic function based on the at least one set of inputs; and

a complementary logic gate connected to the first power supply domain and the at least two cross coupled FETs, wherein the complementary logic gate is comprised of at least one nFET and configured to generate a complement of the logic function based on the at least one set of inputs,

wherein the pFETs and nFETs are thin-oxide FETs.

2. The circuit of claim 1, wherein:

a source of one of the at least two cross coupled FETs is connected to the second power supply domain;

a source of another of the at least two cross coupled FETs is connected to the second power supply domain;

a drain of the one of the at least two cross coupled FETs is connected to a drain of the true logic gate; and

a drain of the another of the at least two cross coupled FETs is connected to a drain of the complementary logic gate.

3. The circuit of claim 2, wherein the first power supply domain and the second power supply domain provide different voltage levels.

4. The circuit of claim 3, wherein:

a source of the true logic gate is connected to ground; and

a source of the complementary logic gate is connected to ground.

5. The circuit of claim 1, further comprising a protection circuit positioned between the at least two cross coupled FETs and the true and complementary logic gates.

6. The circuit of claim 5, wherein the protection circuit comprises at least four thin-oxide FETs.

7. A structure, comprising:

at least one set of inputs from a first power supply domain;

at least two cross coupled field effect transistors (FETs) connected to a second power supply domain;

a true logic gate connected to the first power supply domain and the at least two cross coupled FETs, wherein the true logic gate is configured to generate a logic function based on the at least one set of inputs;

a complementary logic gate connected to the first power supply domain and the at least two cross coupled FETs, wherein the complementary logic gate is configured to generate a complement of the logic function based on the at least one set of inputs; and

a protection interface positioned between the at least two cross coupled FETs and the true and complementary logic gates, wherein the protection interface is controlled by high and low protection analog voltages.

8. The structure of claim 7, wherein the first power supply domain and the second power supply domain provide different voltage levels.

9. The structure of claim 8, wherein:

the at least two cross coupled FETs are pFETs;

the true logic gate is comprised of at least one nFET;

the complementary logic gate is comprised of at least one nFET; and

the protection circuit comprises at least two pFETs and at least two nFETs.

10. The structure of claim 9, wherein all of the pFETs and nFETs are thin-oxide FETs.

11. The structure of claim 10, wherein:

a source of one of the at least two cross coupled pFETs is connected to the second power supply domain;

a source of another of the at least two cross coupled pFETs is connected to the second power supply domain;

a drain of the one of the at least two cross coupled pFETs is connected to a source of one of the two pFETs of the protection circuit; and

a drain of the another of the at least two cross coupled pFETs is connected to a source of another of the two pFETs of the protection circuit.

12. The structure of claim 11, wherein:

a drain of the one of the two pFETs of the protection circuit is connected to a source of one of the two nFETs of the protection circuit; and

a drain of the another of the two pFETs of the protection circuit is connected to a source of another of the two nFETs of the protection circuit.

13. The structure of claim 12, wherein:

a drain of the one of the two nFETs of the protection circuit is connected to a drain of the at least one nFET of the true logic gate; and

a drain of the another of the two nFETs of the protection circuit is connected to a drain of the at least one nFET of the complementary logic gate.

14. A structure comprising at least two level shifters configured to receive a set of input vectors in a first voltage domain to create a true and complement output function in a second voltage domain, wherein:

each of the at least two level shifters is powered by the second voltage domain;

each of the at least two level shifters is configured to generate a true and complement sub-function output in the second voltage domain

each of the at least two level shifters comprising a stacking of a number of transistors less than a predetermined number; and

the at least two level shifters are configured to operate in parallel such that each true and complement sub-function output is coupled with one or more AND or OR gates to create the true and complement output function respectively for all combinations of the set of input vectors.

15. The structure of claim 14, wherein the predetermined number is based on providing sufficient voltage headroom for the at least two level shifters to operate in a predetermined technology and the second voltage domain.

16. The structure of claim 15, wherein each of the at least two level shifters comprises a true logic component configured to generate the true sub-function output, and a complementary logic component configured to generate the complementary sub-function output.

17. The structure of claim 16, wherein each of the at least two level shifters further comprises a protection circuit positioned between at least two cross coupled field effect transistors (FETs) and the true and complementary logic components.