Programmable delay circuitry

• US 8,981,848 B2
• Filed: 09/10/2013
• Issued: 03/17/2015
• Est. Priority Date: 04/19/2010
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Kay, Michael R., Gorisse, Philippe, Khlat, Nadim
• Primary Examiner(s): NGUYEN, PATRICIA T
• Application Number:
  US14/022,940
• Publication Number:
  US 20140009200A1
• Time in Patent Office: 553 Days
• Field of Search: 330/280, 327/284, 327/277
• US Class Current: 330/280
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03F 1/0244 Stepped control
• CPC Class Codes: H03F 1/025 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 1/42 Modifications of amplifiers to extend the bandwidth
• CPC Class Codes: H03F 2200/102 A non-specified detector of a signal envelope being used in an amplifying circuit
• CPC Class Codes: H03F 2200/204 A hybrid coupler being used at the output of an amplifier circuit
• CPC Class Codes: H03F 2200/36 the amplifier comprising means for increasing the bandwidth
• CPC Class Codes: H03F 2200/375 Circuitry to compensate the offset being present in an amplifier
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/555 A voltage generating circuit being realised for biasing different circuit elements
• CPC Class Codes: H03F 2200/78 A comparator being used in a controlling circuit of an amplifier
• CPC Class Codes: H03F 2203/45526 the FBC comprising a resistor-capacitor combination and being coupled between the LC and the IC
• CPC Class Codes: H03F 2203/45544 the IC comprising one or more capacitors, e.g. coupling capacitors
• CPC Class Codes: H03F 2203/45594 the IC comprising one or more resistors, which are not biasing resistor
• CPC Class Codes: H03F 2203/45694 the LC comprising more than one shunting resistor
• CPC Class Codes: H03F 2203/45712 the LC comprising a capacitor as shunt
• CPC Class Codes: H03F 2203/45718 the LC comprising a resistor as shunt
• CPC Class Codes: H03F 2203/7221 the gated amplifier being switched on or off by a switch at the output of the amplifier
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/245 : with semiconductor devices only
• CPC Class Codes: H03F 3/3022 : CMOS common source output SEPP amplifiers H03F3/3008 takes precedence
• CPC Class Codes: H03F 3/45475 : using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/505 : with field-effect devices
• CPC Class Codes: H03F 3/72 : Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03K 5/14 : by the use of delay lines H03K5/133 takes precedence

Abstract

Programmable delay circuitry, which includes an input buffer circuit and variable delay circuitry, is disclosed. The variable delay circuitry includes an input stage, a correction start voltage circuit, and a variable delay capacitor. The input buffer circuit is coupled to the input stage, the correction start voltage circuit is coupled to the input stage, and the variable delay capacitor is coupled to the input stage. The programmable delay circuitry is configured to provide a fixed time delay and a variable time delay.

Claims

1. Programmable delay circuitry comprising:

an input buffer circuit coupled to an input stage; and

variable delay circuitry comprising;

the input stage comprising a first P-type field effect transistor element (PFET) and a first N-type field effect transistor element (NFET), such that a drain of the first PFET and a drain of the first NFET are both coupled to a variable delay capacitor;

a correction start voltage circuit coupled to the input stage; and

the variable delay capacitor coupled to the input stage, wherein the programmable delay circuitry is configured to provide a fixed time delay and a variable time delay.

2. The programmable delay circuitry of claim 1 wherein the input buffer circuit is configured to provide a first portion of the fixed time delay and the variable delay circuitry is configured to provide a second portion of the fixed time delay and the variable time delay.

3. The programmable delay circuitry of claim 1 further configured to receive and delay an input voltage to provide an output voltage.

4. The programmable delay circuitry of claim 1 wherein the correction start voltage circuit is configured to provide a first known voltage level at a source of the first PFET while the first PFET is in a non-conducting state.

5. The programmable delay circuitry of claim 4 wherein the first known voltage level is substantially equal to a ground.

6. The programmable delay circuitry of claim 4 wherein the correction start voltage circuit is configured to provide a second known voltage level at a source of the first NFET while the first NFET is in a non-conducting state.

7. The programmable delay circuitry of claim 6 wherein the second known voltage level is substantially equal to a circuit supply voltage.

8. The programmable delay circuitry of claim 1 wherein the input stage further comprises a second PFET and a second NFET, such that the correction start voltage circuit comprises interconnections of the first PFET and the first NFET to the second PFET and the second NFET.

9. The programmable delay circuitry of claim 8 wherein corresponding gates of each of the first PFET, the first NFET, the second PFET, and the second NFET are coupled to one another.

10. The programmable delay circuitry of claim 8 wherein a source of the first PFET is coupled to a drain of the second NFET, and a source of the first NFET is coupled to a drain of the second PFET.

14. The programmable delay circuitry of claim 1 wherein the variable delay circuitry further comprises an output buffer stage coupled to the variable delay capacitor.

15. The programmable delay circuitry of claim 1 wherein the variable delay capacitor is configured as a programmable capacitor array.

16. The programmable delay circuitry of claim 15 wherein the programmable capacitor array is a binary weighted capacitor array.

17. The programmable delay circuitry of claim 15 wherein the programmable capacitor array comprises a plurality of capacitive elements.

18. The programmable delay circuitry of claim 17 wherein the programmable capacitor array is a linear capacitor array, such that each of the plurality of capacitive elements has about a same value.

19. The programmable delay circuitry of claim 1 wherein the variable delay capacitor is configured to increase as a value of a binary capacitor control word increases.

20. The programmable delay circuitry of claim 1 wherein the variable delay capacitor comprises a programmable varactor.

11. Programmable delay circuitry comprising:

a voltage divider circuit;

a bias current and minor circuit, such that the voltage divider circuit is coupled to the bias current and minor circuit, and the bias current and minor circuit is coupled to an input stage;

an input buffer circuit coupled to the input stage; and

variable delay circuitry comprising;

the input stage;

a correction start voltage circuit coupled to the input stage; and

a variable delay capacitor coupled to the input stage, wherein the programmable delay circuitry is configured to provide a fixed time delay and a variable time delay.

12. The programmable delay circuitry of claim 11 wherein the variable time delay is based on a first bias current and a second bias current in the variable delay circuitry, such that the first bias current and the second bias current are based on the voltage divider circuit and the bias current and mirror circuit.

13. The programmable delay circuitry of claim 11 wherein the voltage divider circuit and the bias current and mirror circuit are configured to reduce changes in the variable time delay due to changes in a voltage level of a circuit supply voltage.

21. A method comprising:

providing an input buffer circuit, which is coupled to an input stage;

providing variable delay circuitry, which comprises;

the input stage comprising a first P-type field effect transistor element (PFET) and a first N-type field effect transistor element (NFET), such that a drain of the first PFET and a drain of the first NFET are both coupled to a variable delay capacitor;

a correction start voltage circuit coupled to the input stage; and

the variable delay capacitor coupled to the input stage; and

providing a fixed time delay and a variable time delay.

22. The method of claim 21 further comprising reducing changes in the variable time delay due to changes in a voltage level of a circuit supply voltage.