Semiconductor device and method of forming RF balun having reduced capacitive coupling and high CMRR

• US 8,981,866 B2
• Filed: 08/09/2012
• Issued: 03/17/2015
• Est. Priority Date: 03/30/2010
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Frye, Robert C., Liu, Kai
• Primary Examiner(s): Takaoka, Dean O
• Application Number:
  US13/571,068
• Publication Number:
  US 20120299151A1
• Time in Patent Office: 950 Days
• Field of Search: 333/25, 333/26, 333/238
• US Class Current: 333/25
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/30107 Inductance
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A semiconductor device has an RF balun formed over a substrate. The RF balun includes a first conductive trace wound to exhibit inductive properties with a first end coupled to a first terminal of the semiconductor device and second end coupled to a second terminal of the semiconductor device. A first capacitor is coupled between the first and second ends of the first conductive trace. A second conductive trace is wound to exhibit inductive properties with a first end coupled to a third terminal of the semiconductor device and second end coupled to a fourth terminal of the semiconductor device. The first conductive trace is formed completely within the second conductive trace. The first conductive trace and second conductive trace can have an oval, circular, or polygonal shape separated by 50 micrometers. A second capacitor is coupled between the first and second ends of the second conductive trace.

Claims

1. A method of making a semiconductor device, comprising:

providing a substrate;

forming an inner conductive trace over the substrate and wound to exhibit an inductive property including a first end coupled to a first terminal of the semiconductor device and a second end coupled to a second terminal of the semiconductor device; and

forming an outer conductive trace over the substrate completely around the inner conductive trace and wound to exhibit an inductive property including a distance separating the inner conductive trace and outer conductive trace to reduce capacitive coupling, a first end coupled to a third terminal of the semiconductor device, and a second end coupled to a fourth terminal of the semiconductor device.

2. The method of claim 1, wherein the inner conductive trace and outer conductive trace are separated by 50 micrometers to reduce capacitive and inductive coupling.

3. The method of claim 1, wherein the inner conductive trace and outer conductive trace have a coupling coefficient between 0.2 and 0.45.

4. The method of claim 1, further including:

forming a first capacitor over the substrate and coupled between the first and second ends of the inner conductive trace; and

forming a second capacitor over the substrate and coupled between the first and second ends of the outer conductive trace.

5. The method of claim 1, wherein the inner conductive trace and outer conductive traces each have an oval, circular, or polygonal shape.

6. The method of claim 1, further including:

providing a center tap midway between the first and second ends of the outer conductive trace; and

applying a DC bias to the center tap.

7. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first conductive trace encircling a portion of the substrate and wound in a coil to exhibit an inductive property;

forming a second conductive trace over the substrate encircling the first conductive trace and wound in a coil to exhibit an inductive property;

providing a center tap midway between first and second ends of the second conductive trace; and

applying a DC bias to the center tap.

8. The method of claim 7, wherein the first conductive trace and second conductive trace are separated by 50 micrometers to reduce capacitive and inductive coupling.

9. The method of claim 7, wherein the first conductive trace and second conductive trace have a coupling coefficient between 0.2 and 0.45.

10. The method of claim 7, further including:

forming a first capacitor over the substrate and coupled between first and second ends of the first conductive trace; and

forming a second capacitor over the substrate and coupled between first and second ends of the second conductive trace.

11. The method of claim 7, wherein a first end of the first conductive trace is coupled to a first terminal of the semiconductor device, a second end of the first conductive trace is coupled to a second terminal of the semiconductor device, a first end of the second conductive trace is coupled to a third terminal of the semiconductor device, and a second end of the second conductive trace is coupled to a fourth terminal of the semiconductor device.

12. The method of claim 7, wherein the first conductive trace and second conductive traces each have an oval, circular, or polygonal shape.

13. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first inductor over the substrate; and

forming a second inductor over the substrate with the first inductor disposed within the second inductor and separated from the second inductor by a distance to reduce coupling.

14. The method of claim 13, further including:

forming a first capacitor over the substrate and coupled between first and second ends of the first inductor; and

forming a second capacitor over the substrate and coupled between first and second ends of the second inductor.

15. The method of claim 13, wherein forming the first inductor and second inductor includes:

forming a first conductive trace over the substrate and wound to exhibit an inductive property; and

forming a second conductive trace over the substrate and wound to exhibit an inductive property with the first conductive trace disposed within the second conductive trace.

16. The method of claim 15, wherein the first conductive trace and second conductive traces each have an oval, circular, or polygonal shape.

17. The method of claim 13, wherein the first inductor and second inductor are separated by 50 micrometers to reduce capacitive and inductive coupling.

18. The method of claim 13, wherein the first inductor and second inductor have a coupling coefficient between 0.2 and 0.45.

19. A semiconductor device, comprising:

a substrate;

a first conductive trace formed over the substrate and wound to exhibit an inductive property; and

a second conductive trace formed over the substrate and wound to exhibit an inductive property with the first conductive trace completely encircled by the second conductive trace.

20. The semiconductor device of claim 19, wherein the first conductive trace and second conductive traces each have an oval, circular, or polygonal shape.

21. The semiconductor device of claim 19, wherein the first conductive trace and second conductive trace are separated by 50 micrometers to reduce capacitive and inductive coupling.

22. The semiconductor device of claim 19, wherein the first conductive trace and second conductive trace have a coupling coefficient between 0.2 and 0.45.

23. The semiconductor device of claim 19, further including:

forming a first capacitor over the substrate and coupled between first and second ends of the first conductive trace; and

forming a second capacitor over the substrate and coupled between first and second ends of the second conductive trace.

24. The semiconductor device of claim 19, wherein a first end of the first conductive trace is coupled to a first terminal of the semiconductor device, a second end of the first conductive trace is coupled to a second terminal of the semiconductor device, a first end of the second conductive trace is coupled to a third terminal of the semiconductor device, and a second end of the second conductive trace is coupled to a fourth terminal of the semiconductor device.