Memory system with sectional data lines

• US 8,982,597 B2
• Filed: 01/31/2012
• Issued: 03/17/2015
• Est. Priority Date: 08/25/2008
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Yan, Tianhong, Fasoli, Luca
• Primary Examiner(s): Norman, James G
• Application Number:
  US13/362,320
• Publication Number:
  US 20120170347A1
• Time in Patent Office: 1,141 Days
• Field of Search: None
• US Class Current: 365/51
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits

Abstract

The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.

Claims

1. A data storage system, comprising:

a memory array including a plurality of data storage elements;

a plurality of signal lines positioned within the memory array including the plurality of data storage elements and in communication with the plurality of data storage elements;

a plurality of local data lines outside the memory array including the plurality of data storage elements, different subsets of the local data lines are in selective communication with different subsets of the data storage elements via the signal lines;

a plurality of global data lines outside of the memory array including the plurality of data storage elements and in selective communication with multiple subsets of the local data lines, the local data lines are positioned between the memory array including the plurality of data storage elements and a substrate for the data storage system;

a first group of selection circuits connected to the signal lines and the local data lines to selectively electrically connect the signal lines to the local data lines;

a second group of selection circuits connected to the subsets of local data lines and the global data lines to selectively electrically connect the subsets of local data lines to the global data lines;

control circuitry connected to the global data lines;

the local data lines are positioned in at least one metal layer below the memory array including the plurality of data storage elements and above the substrate which is below the memory array, the control circuitry connected to the global data lines, being positioned on the substrate; and

the global data lines are positioned in at least one metal layer above the memory array including the plurality of data storage elements.

2. The data storage system of claim 1, wherein:

the signal lines are bit lines; and

the memory array comprises a monolithic three-dimensional memory array.

3. The data storage system of claim 1, wherein:

the memory array including the plurality of data storage elements are arranged into multiple bays;

each bay includes multiple blocks;

each block includes a subset of the plurality of data storage elements; and

each block is connected to a different subset of the local data lines via an associated subset of the signal lines and an associated subset of the first group of selection circuits.

4. The data storage system of claim 1, wherein:

the memory array including the plurality of data storage elements are arranged into multiple bays;

each bay includes multiple blocks;

each block includes a subset of the plurality of data storage elements;

the blocks are grouped such that each group includes multiple blocks; and

each group of blocks is connected to a different subset of the local data lines via an associated subset of the signal lines and an associated subset of the first group of selection circuits.

5. The data storage system of claim 1, wherein:

a subset of the signal lines are below some of the data storage elements and above some of the data storage elements.

6. The data storage system of claim 1 further comprising:

the data storage elements are arranged in three-dimensions.

7. The data storage system of claim 1 further comprising:

the data storage elements are arranged in a three-dimensional memory structure.

8. The data storage system of claim 1, wherein:

the memory array including the plurality of data storage elements is a three-dimensional memory array including the data storage elements.

9. The data storage system of claim 1, wherein:

the memory array comprises a monolithic three-dimensional memory array.

10. A data storage system, comprising:

a memory array including a plurality of data storage elements;

a plurality of signal lines positioned within the memory array including the plurality of data storage elements and in communication with the data storage elements;

a plurality of local data lines outside the memory array including the plurality of data storage elements and in selective communication with the signal lines, a first subset of the local data lines are in selective communication with a first subset of the data storage elements and not in communication with other data storage elements, a second subset of the local data lines are in selective communication with a second subset of the data storage elements and not in communication with other data storage elements;

a plurality of global data lines outside of the memory array including the plurality of data storage elements, the global data lines are in selective communication with the first subset of the local data lines and the second subset of the local data lines;

a first group of selection circuits connected to the signal lines and the local data lines to selectively electrically connect the signal lines to the local data lines;

a second group of selection circuits connected to the subsets of local data lines and the global data lines to selectively electrically connect the subsets of local data lines to the global data lines;

control circuitry connected to the global data lines;

a substrate, the control circuitry is positioned on the substrate;

the local data lines are positioned in at least one metal layer below the memory array including the plurality of data storage elements and above the substrate which is below the memory array; and

the global data lines are positioned in at least one metal layer above the memory array including the plurality of data storage elements.

11. The data storage system of claim 10 further comprising:

the data storage elements are arranged in three-dimensions.

12. The data storage system of claim 10 further comprising:

the data storage elements are arranged in a three-dimensional memory structure.

13. The data storage system of claim 10 further comprising:

the memory array including the plurality of data storage elements is a three-dimensional memory array including the data storage elements.

14. The data storage system of claim 10, wherein:

the memory array comprises a monolithic three-dimensional memory array.

15. A data storage system, comprising:

a memory array including a plurality of data storage elements;

a plurality of bit lines positioned within the memory array including the plurality of data storage elements and in communication with the plurality of data storage elements;

a plurality of local data lines outside the memory array including the plurality of data storage elements, different subsets of the local data lines are in selective communication with different subsets of the data storage elements via the bit lines;

a plurality of global data lines outside of the plurality of data storage elements in a top layer above the memory array including the plurality of data storage elements and in selective communication with multiple subsets of the local data lines, the local data lines are positioned in one or more layers between the memory array including the plurality of data storage elements and a substrate for the data storage system below the memory array;

a first group of selection circuits connected to the bit lines and the local data lines to selectively electrically connect the bit lines to the local data lines;

a second group of selection circuits connected to the subsets of local data lines and the global data lines to selectively electrically connect the subsets of local data lines to the global data lines; and

control circuitry connected to the global data lines, being positioned on the substrate.

16. The data storage system of claim 15 further comprising:

the data storage elements are arranged in three-dimensions.

17. The data storage system of claim 15 further comprising:

the data storage elements are arranged in a three-dimensional memory structure.

18. The data storage system of claim 15 further comprising:

the memory array including the plurality of data storage elements is a three-dimensional memory array including the data storage elements.

19. The data storage system of claim 15, wherein:

the memory array comprises a monolithic three-dimensional memory array.