Phase change memory device having multi-level and method of driving the same

• US 8,982,605 B2
• Filed: 09/23/2014
• Issued: 03/17/2015
• Est. Priority Date: 06/15/2009
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Park, Hae Chan, Lee, Se Ho
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US14/494,355
• Publication Number:
  US 20150009752A1
• Time in Patent Office: 175 Days
• Field of Search: 365/148, 365/63, 365/72, 365/175, 365/163, 365/231
• US Class Current: 365/148
• CPC Class Codes: G11C 11/21 using electric elements
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0042 Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]
• CPC Class Codes: G11C 2013/0078 Write using current through the cell
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 2213/74 Array wherein each memory cell has more than one access device
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors

Abstract

A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level.

Claims

1. A phase change memory device comprising:

a semiconductor substrate having peripheral areas and a cell area therebetween;

first and second word line select switches on an upper part of the semiconductor substrate in the peripheral areas;

first word lines electrically connected to the first word line select switches, the first word lines on the upper part of the semiconductor substrate on which the first word line select switches are formed;

first diodes on the upper parts of the first word lines;

second word lines on the upper parts of the first diodes;

second diodes on the upper parts of the second word lines correspondingly aligned over the first diodes;

heating electrodes correspondingly coupled to upper parts of the second diodes;

phase change patterns correspondingly coupled to upper parts of the heating electrodes; and

bit lines correspondingly coupled to upper parts of the phase change patterns.

2. The phase change memory device of claim 1, wherein the first and second word line select switches are MOS transistors.

3. The phase change memory device of claim 1, further comprising:

a first insulating layer interposed on the semiconductor substrate on which the first and second word line select switches are formed;

a second insulating layer interposed between the first word line and the second word line;

a third insulating layer interposed between the second word line and the heating electrode; and

t

a fourth insulating layer interposed between the heating electrode and the bit line.

4. The phase change memory device of claim 1, wherein at least one of the first and second word lines comprises a silicon containing a conductive material.

5. The phase change memory device of claim 4, wherein at least one of the first and second pn diodes is a silicon base schottky diode.

6. The phase change memory device of claim 1, wherein at least one of the first and second word lines comprises a metal containing material.

7. The phase change memory device of claim 6, wherein the first or second on diodes are metal schottky diodes.

8. The phase change memory device of claim 1, wherein a lower part of the first word line is formed with devices configuring peripheral circuits.