Managing non-volatile media

• US 8,982,619 B2
• Filed: 09/15/2014
• Issued: 03/17/2015
• Est. Priority Date: 01/27/2010
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Intelligent Intellectual Property Holdings LLC
• Inventors: Strasser, John, Flynn, David, Fillingim, Jeremy, Wood, Robert, Hyun, Jea, Sun, Hairong
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US14/486,974
• Publication Number:
  US 20150006984A1
• Time in Patent Office: 183 Days
• Field of Search: 365/185.03, 365/185.09, 365/185.11, 365/185.12, 365/185.17, 365/185.18, 365/185.24, 365/185.29, 365/185.33
• US Class Current: 365/185.03
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/26 Functional testing
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 16/00 Erasable programmable read-only memories G11C14/00 takes precedence
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/026 in sense amplifiers
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/50016 of retention

Abstract

Apparatuses, systems, and methods are disclosed to manage non-volatile media. A method includes determining a configuration parameter for a set of storage cells of a non-volatile recording medium. A method includes reading data from a set of storage cells using a determined configuration parameter. A method includes adjusting a configuration parameter based on read data.

Claims

1. A method comprising:

determining a configuration parameter for a set of storage cells of a solid state recording medium;

reading data from the set of storage cells using the determined configuration parameter; and

adjusting the configuration parameter based on the read data.

2. The method of claim 1, further comprising:

re-reading the data from the set of storage cells using the adjusted configuration parameter; and

readjusting the configuration parameter based on the re-read data.

3. The method of claim 1, wherein adjusting the configuration parameter based on the read data is performed reactively in response to a trigger and the read data comprises closed loop feedback data from the set of storage cells.

4. The method of claim 1, wherein determining the configuration parameter is based on one or more media characteristics for the set of storage cells such that the configuration parameter is determined proactively in an open loop manner without feedback from the set of storage cells.

5. The method of claim 1, wherein the configuration parameter comprises a read voltage threshold for the set of storage cells.

6. The method of claim 1, further comprising:

storing different configuration parameters for different sub-groupings of the set of storage cells; and

reconfiguring the entire set of storage cells to use one of the different configuration parameters in response to a storage request for a sub-grouping associated with the one of the different configuration parameters.

7. The method of claim 1, wherein adjusting the configuration parameter comprises adjusting a guard band, the guard band comprising a separation distance between voltage abodes for the set of storage cells.

8. The method of claim 1, wherein adjusting the configuration parameter comprises adjusting multiple read voltage thresholds for each storage cell of the set of storage cells.

9. The method of claim 8, wherein the multiple read voltage thresholds are adjusted using a single command.

10. The method of claim 1, wherein adjusting the configuration parameter comprises reducing a program voltage for the set of storage cells over time.

11. The method of claim 1, further comprising decreasing a data refresh interval for the set of storage cells over time, the data refresh interval comprising an interval at which a storage capacity recovery operation is performed for the set of storage cells.

12. An apparatus comprising:

a configuration parameter module configured to determine a read voltage threshold for one or more NAND flash storage cells;

a storage cell configuration module configured to configure the one or more storage cells to use the determined read voltage threshold; and

an adjustment module configured to adjust the read voltage threshold based on closed loop feedback from the one or more NAND flash storage cells.

13. The apparatus of claim 12, wherein the adjustment module is configured to make a same adjustment to the read voltage threshold for one or more of an erase block, a page, a set of pages, an error-correcting code (ECC) codeword, a division within a page, a die, a plane of a die, and a chip comprising the one or more NAND flash storage cells.

14. The apparatus of claim 12, further comprising a data set read module configured to read data from the one or more NAND flash storage cells in response to a trigger, the read data comprising the closed loop feedback.

15. The apparatus of claim 14, wherein the trigger comprises one or more of a read request for the set of storage cells, an uncorrectable error for the data of the set of storage cells, a startup operation for a device comprising the set of storage cells, a time interval, and a regular shutdown operation for a device comprising the set of storage cells.

16. The apparatus of claim 12, wherein the adjustment module is configured to stop adjusting the read voltage threshold in response to a retry threshold being satisfied.

17. The apparatus of claim 12, wherein the adjustment module is configured to determine whether to make an adjustment to the read voltage threshold based on one or more risk factors associated with the adjustment, the one or more risk factors comprising one or more of an error rate, an erase cycle count, a storage request latency, an age, and a number of previous adjustments for the one or more NAND flash storage cells.

18. An apparatus comprising:

means for detecting an uncorrectable error in data read from a set of non-volatile memory cells; and

means for iteratively adjusting one or more read voltage thresholds for the set of memory cells and re-reading the data from the set of memory cells until the uncorrectable error in the data is correctable.

19. The apparatus of claim 18, further comprising means for determining an initial value for the one or more read voltage thresholds based on one or more media characteristics for the set of memory cells, the initial value being iteratively adjusted.

20. The apparatus of claim 18, wherein the data read from the set of non-volatile memory cells comprises a subset of data stored by the set of non-volatile memory cells and the one or more read voltage thresholds are adjusted based on the subset of data.