Jitter tolerant receiver

• US 8,982,999 B2
• Filed: 09/30/2012
• Issued: 03/17/2015
• Est. Priority Date: 09/30/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bhagavathula, Kiriti, Zhang, Chunyu, Peterson, Steven A.
• Primary Examiner(s): Corrielus, Jean B
• Application Number:
  US13/632,082
• Publication Number:
  US 20140092951A1
• Time in Patent Office: 898 Days
• Field of Search: 375/316, 375/355, 375/359, 375/361, 375/371, 327165-166, 327/291, 326/52, 326/54, 326/93, 326/136
• US Class Current: 375/316
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices
• CPC Class Codes: H04L 25/4908 using mBnB codes
• CPC Class Codes: H04L 7/0066 detection of error based on transmission code rule

Abstract

An embodiment of the invention includes a receiver with reduced error terms and incoming jitter tracking that improves jitter tolerance. An embodiment provides these benefits based on a voltage integrator that recovers data and clock information from incoming signals without use of a PLL, PI, CDR, and the like. An embodiment provides these benefits based on a time integrator that recovers, using digital logic, data and clock information from incoming signals without use of a PLL, PI, CDR, and the like. Other embodiments are described herein.

Claims

1. A receiver comprising:

at least one memory configured to receive first and second signals at a single instant in time in response to a transmission from a transmitter, the first and second signals being run length limited (RLL) encoded; and

receiver logic, coupled to the at least one memory, to determine both a clock signal and a data signal from the first signal independently of timing information from phase locked loop (PLL) logic;

wherein the receiver logic is to determine a bit length of a symbol included in the second signal based on the clock signal from the first signal.

2. The receiver of claim 1, wherein the receiver logic includes no PLL logic.

3. The receiver of claim 1, wherein the receiver logic is to determine the clock and data signals from the first signal independently of a closed feedback loop.

4. The receiver of claim 1, wherein the first signal is a polar opposite of the second signal.

5. The receiver of claim 1, wherein the receiver logic is to:

derive a first derived signal from the first signal and a second derived signal from the second signal;

determine a concatenation of the first and second derived signals; and

determine the clock and data signals based on the concatenation.

6. The receiver of claim 5, wherein the concatenation is based on one of an XOR and an XNOR logical operation.

7. The receiver of claim 1, wherein the receiver logic is to:

derive a first derived signal from the first signal and a second derived signal from the second signal;

integrate the first derived signal to determine a first integrated signal;

sample the first integrated signal to determine a first sample;

compare the first sample to a reference signal to determine a first comparison; and

determine at least one of the bit length of the symbol and an additional bit length of an additional symbol included in one of the first and second signals based on the first comparison.

8. The receiver of claim 7, wherein the receiver logic is to integrate one of voltage and time of the first derived signal to determine the first integrated signal.

9. The receiver of claim 1, wherein the first and second signals are RLL encoded at an upper limit N of consecutive like bit values, and the receiver logic is to:

derive a first derived signal from the first signal and a second derived signal from the second signal;

integrate the first derived signal to determine a first integrated signal;

sample the first integrated signal to determine a first sample;

compare the first sample to N reference signals to determine a first comparison; and

determine at least one of the bit length of the symbol and an additional bit length of an additional symbol included in one of the first and second signals based on the first comparison;

wherein N is greater than 1.

10. The receiver of claim 9, wherein the N reference signals are not all equally spaced from one another.

11. The receiver of claim 1 wherein the transmission includes jitter.

12. The receiver of claim 1, wherein the receiver logic is to determine at least one of the bit length of the symbol and an additional bit length of an additional symbol included in the second signal on a symbol-by-symbol basis.

13. The receiver of claim 1, wherein the receiver logic is to determine at least one of the bit length of the symbol and an additional bit length of an additional symbol included in the second signal independently of any other symbol included in the transmission.

14. The receiver of claim 1, wherein the receiver logic is to determine at least one of the bit length of the symbol and an additional bit length of an additional symbol included in one of the first and second signals independently of eye tracking.

15. The receiver of claim 1, wherein the receiver logic is to:

derive a first derived signal from the first signal and a second derived signal from the second signal;

integrate the first derived signal via a first integrator and the second signal via a second integrator; and

reset the first integrator in parallel with integrating with the second integrator.

16. A receiver comprising:

equalization logic;

amplifier logic, coupled to the equalization logic, to amplify first and second signals, which are both to be stored in the receiver at a single instant in time, in response to a transmission from a transmitter, the first and second signals being run length limited (RLL) encoded;

receiver logic, coupled to the amplifier logic, to determine both a clock signal and a data signal from the first signal independently of timing information from phase locked loop (PLL) logic; and

first and second integrators, included in the receiver logic to respectively integrate a first derived signal, derived from the first signal, and a second derived signal, derived from the second signal;

wherein the first integrator is to reset in parallel with the second integrator integrating.

17. The receiver of claim 16, wherein the receiver logic includes:

a first plurality of flip flops for the first signal and a second plurality of flip flops for the second signal;

a first logic gate to determine the first derivative signal from the first signal and a second logic gate to determine the second derivative signal from the second signal; and

a third logic gate to concatenate the first and second derivative signals to determine the clock signal.

18. The receiver of claim 16, wherein the receiver logic includes a first delay chain that is to delay a symbol included in the first chain in proportion to a total bit length of the symbol.

19. An apparatus comprising:

receiving logic configured to receive a differential signal to represent a plurality of symbols;

amplifier logic coupled to the receiving logic, the amplifier logic to amplify the differential signal to obtain an amplified differential signal;

integration logic coupled to the amplifier logic, the integration logic to integrate the amplified differential signal to obtain an integrated representation of the differential signal; and

sampling logic coupled to the amplifier logic and the integration logic, the sampling logic to cause a sample of the integrated representation of the differential signal based on the amplified differential signal.

20. The apparatus of claim 19, wherein the sample of the integrated representation of the differential signal includes a comparison of the integrated representation of the differential signal to at least one threshold value to determine a symbol length of the plurality of symbols.

21. The apparatus of claim 19, wherein the receiving logic, amplifier logic, integration logic, and sampling logic are included in a system on chip (SOC) integrated circuit within a user endpoint device, the SOC coupled to a radio and antenna and a controller to receive input from a touch enabled display of the user endpoint device.

22. A method comprising:

receiving a differential signal to represent a plurality of symbols;

amplifying the differential signal to obtain an amplified differential signal;

integrating the amplified differential signal to obtain an integrated representation of the differential signal; and

sampling the integrated representation of the different signal based on the amplified differential signal.

23. The method of claim 22 comprising:

determining a comparison of the integrated representation of the differential signal to at least one threshold value in response to the sampling; and

determining a symbol length of a symbol included in the plurality of symbols based on the comparison.

24. The method of claim 22 comprising:

receiving the differential signal via receiving logic, amplifying the differential signal via amplifier logic, integrating the amplified differential signal via integration logic, and sampling the integrated representation of the different signal via sampling logic;

wherein the receiving logic, amplifier logic, integration logic, and sampling logic are included in a system on chip (SOC) integrated circuit within a user endpoint device, the SOC coupled to a radio and antenna and a controller to receive input from a touch enabled display of the user endpoint device.