Memory cell operation

• US 8,984,214 B2
• Filed: 03/14/2013
• Issued: 03/17/2015
• Est. Priority Date: 09/26/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Chen, Frank, Chen, Liang (Leo)
• Primary Examiner(s): Gu, Shawn X
• Application Number:
  US13/827,135
• Publication Number:
  US 20130198452A1
• Time in Patent Office: 733 Days
• Field of Search: None
• US Class Current: 711/103
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

The present disclosure includes memory devices and systems having memory cells, as well as methods for operating the memory cells. One or more methods for operating memory cells includes determining age information for a portion of the memory cells and communicating a command set for the portion of the memory cells, the command set including the age information.

Claims

1. A method for operating memory cells of a memory device, comprising:

receiving, by the memory device, a wear state for the memory cells from a memory access device;

determining, by the memory device, a set of operating parameters for the memory cells responsive to the received wear state,

wherein the wear state corresponds to a quantity of erase pulses used to accomplish a verified erasure of the memory cells.

2. The method of claim 1, wherein receiving the wear state includes receiving the wear state from available bits within a pre-existing legacy-compatible quantity of address cycles.

3. The method of claim 1, wherein receiving the wear state includes receiving wear cycle information from available bits within a pre-existing legacy-compatible quantity of address cycles.

4. The method of claim 1, wherein receiving the wear state includes receiving the wear state from available bits within a pre-existing legacy-compatible quantity of command cycles.

5. The method of claim 1, wherein receiving the wear state includes receiving wear cycle information from available bits within a pre-existing legacy-compatible quantity of command cycles.

6. The method of claim 1, the determined set of operating parameters causes the memory cells to expend useful life at a different rate.

7. The method of claim 1, wherein determining the set of operating parameters includes determining at least one of a programming pulse voltage magnitude, a programming pulse duration, a programming pulse frequency, and a quantity of programming pulses.

8. A method for operating memory cells of a memory device, comprising:

determining, by a memory access device, a wear state for the memory cells; and

communicating the wear state from the memory access device to the memory device; and

determining, by the memory device, a set of operating parameters for the memory cells in response to the determined wear state,

wherein determining the wear state for the memory cells includes evaluating characteristics of the memory device corresponding to the wear state, and

wherein evaluating characteristics of the memory device corresponding to the wear state includes measuring a quantity of erase pulses used to accomplish a verified erasure of the memory cells.

9. The method of claim 8, wherein communicating the wear state includes providing a quantity of wear cycles to the memory device with each read operation.

10. The method of claim 8, wherein communicating the wear state includes providing a quantity of wear cycles to the memory device with each program operation.

11. The method of claim 8, wherein communicating the wear state includes providing a quantity of wear cycles to the memory device with each erase operation.

12. The method of claim 8, further comprising compensating for memory device performance changes corresponding to the wear state.

13. A method for operating memory cells of a memory device, comprising:

determining, by a memory access device, a wear state for the memory cells; and

communicating the wear state from the memory access device to the memory device; and

determining, by the memory device, a set of operating parameters for the memory cells in response to the determined wear state,

wherein communicating the wear state from the memory access device to the memory device includes using available bits within a pre-existing legacy-compatible quantity of address cycles to communicate the wear state and/or wear cycle information.

14. A method for operating memory cells of a memory device, comprising:

determining, by a memory access device, a wear state for the memory cells; and

communicating the wear state from the memory access device to the memory device; and

determining, by the memory device, a set of operating parameters for the memory cells in response to the determined wear state,

wherein communicating the wear state from the memory access device to the memory device includes using available bits within a pre-existing legacy-compatible quantity of command cycles to communicate the wear state and/or wear cycle information.

15. A memory device, comprising:

an array of memory cells; and

control circuitry coupled to the array, and adapted to;

receive a wear state for the memory cells from a memory access device; and

determine at least one operating parameter for the memory cells in response to the received wear state,

wherein the wear state corresponds to a quantity of erase pulses used to accomplish a verified erasure of the memory cells.

16. The method of claim 15, wherein the control circuitry is further adapted to determine the at least one operating parameter so as to minimize an expected Vt drift for a particular wear state of the memory cells.

17. The memory device of claim 15, wherein the control circuitry is further adapted to implement slower speed operation of the memory cells responsive to the received wear state.

18. The memory device of claim 15, wherein the control circuitry is further adapted to implement higher reliability operation of the memory cells responsive to the received wear state.

19. The memory device of claim 15, wherein the control circuitry is further adapted to change at least one operating parameter for the memory cells in response to the received wear state.

20. The memory device of claim 15, wherein the control circuitry is further adapted to compensate for memory device performance changes corresponding to the received wear state.