Memory system and memory management method including the same
First Claim
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1. A method for sharing a memory between a first processor and a second processor, comprising:
- transmitting a token from a first processor to a second processor;
accessing the memory by the second processor if the token is received, the memory being accessible by one of the first processor and the second processor at a time;
after accessing the memory, transmitting the token from the second processor to the first processor; and
accessing the memory by the first processor if the token is received,wherein if the token is not received by the second processor, sending a request signal for the token from the second processor back to the first processor, starting a timer, and if the timer expires prior to the token being transmitted to the second processor, generating a substitute token by the second processor, andwherein the token is transmitted between the first and second processors via a communication channel directly connected between the first and second processors, the communication channel having no intermediary token storage device between the first and second processors.
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Abstract
A multi-processor system includes a first processor, a second processor communicable with the first processor, a first non-volatile memory for storing first codes and second codes to respectively boot the first and second processors, the first memory communicable with the first processor, a second volatile memory designated for the first processor, a third volatile memory designated for the second processor, and a fourth volatile memory shared by the first and second processors.
23 Citations
13 Claims
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1. A method for sharing a memory between a first processor and a second processor, comprising:
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transmitting a token from a first processor to a second processor; accessing the memory by the second processor if the token is received, the memory being accessible by one of the first processor and the second processor at a time; after accessing the memory, transmitting the token from the second processor to the first processor; and accessing the memory by the first processor if the token is received, wherein if the token is not received by the second processor, sending a request signal for the token from the second processor back to the first processor, starting a timer, and if the timer expires prior to the token being transmitted to the second processor, generating a substitute token by the second processor, and wherein the token is transmitted between the first and second processors via a communication channel directly connected between the first and second processors, the communication channel having no intermediary token storage device between the first and second processors. - View Dependent Claims (2, 3, 4, 5)
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6. A multi-processor system comprising:
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a first processor; a second processor; and a dual-port memory connected to each of the first processor and the second processor, memory cells of the dual-port memory being organized into a plurality of banks, at least one bank being accessible exclusively via a first port, at least one bank being accessible exclusive via a second port, and at feast one shared bank being accessible by both the first port and the second port, wherein a token is passable between the first processor and the second processor over a communication channel directly connected between the first processor and the second processor, the communication channel having no intermediary token storage device between the first and second processors, a receipt of the token being indicative of accessibility of the at least one shared bank by either the first processor or the second processor, wherein if the token is not received by the second processor, sending a request signal for the token from the second processor back to the first processor, starting a timer, and if the time expires prior to the token being transmitted to the second processor, generating a substitute token by the second processor, and wherein the dual-port memory comprises a register having flag bits to track the token for access to the at least one shared bank, each of the first processor and the second processor having access to the register to check the flag bits to verify possession of the token and to request the token. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13)
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Specification