ID generation apparatus and method for serially interconnected devices

• US 8,984,249 B2
• Filed: 12/20/2006
• Issued: 03/17/2015
• Est. Priority Date: 12/20/2006
• Status: Active Grant

• Current Assignee: NovaChips Canada Inc. (NovaChips Co., Ltd.)
• Original Assignee: NovaChips Canada Inc. (NovaChips Co., Ltd.)
• Inventors: Pyeon, Hong Beom, Oh, HakJune, Kim, Jin-Ki, Przybylski, Steven
• Primary Examiner(s): Li, Aimee
• Assistant Examiner(s): Thammavong, Prasith
• Application Number:
  US11/613,563
• Publication Number:
  US 20080155219A1
• Time in Patent Office: 3,009 Days
• Field of Search: 711/167
• US Class Current: 711/167
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1003 Interface circuits for daisy chain or ring bus memory arrangements
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

A plurality of memory devices (e.g., DRAMs, SRAMs, NAND Flash, NOR Flash) is serially interconnected. Each of the interconnected devices receives a device identifier (ID) and latches it as its ID. Each device includes a circuit for calculating another ID or an incremented ID to generate it. The generated ID is transferred to another device and the ID is incremented in each of the devices in the serial interconnection. The last device in the interconnection provides a last generated ID that is provided to a memory controller having a recognition circuit that recognizes the total number of the serially interconnected devices, from the provided last generated ID. The recognition circuit recognizes the total output latency of the devices in the serial interconnection.

Claims

1. A system comprising:

a controller,

a plurality of memory devices in a serial interconnection configuration, each of the plurality of memory devices having a select input connection, an input connection, an output connection and an enable input connection, a first one of said plurality of devices being coupled to the controller,

the select input connection of each device being coupled to receive a mode select signal, each device being set in a device identifier production mode in response to the mode select signal,

the input connection of each device being coupled to the output connection of a previous device, the output connection of each device being coupled to the input connection of a subsequent device, the input connection of the first device of the serial interconnection configuration being coupled to receive an initial device identifier from the controller,

the enable input connection of each device being coupled to receive an enable signal from the previous device, the device being enabled to receive a device identifier in response to the enable signal,

each of the plurality of memory devices including;

a producer, set in the ID production mode, configured to produce a device identifier in response to an input device identifier received through its input connection in response to the enable signal, the device identifier produced by the producer of each device to be provided to the subsequent device through its output connection,

the controller including a receiver configured;

to receive the device identifier from a last device of the serial interconnection configuration, and to determine the number of the plurality of memory devices in the serial interconnection configuration in response to the received device identifier.

2. The system of claim 1, wherein the producer comprises:

a device identifier receiver configured to receive the device identifier from the previous device through the input connection thereof;

a device identifier generator configured to generate a device identifier in response to the received device identifier and the received control signal; and

a device identifier provider configured to output the device identifier generated by the device identifier generator.

3. The system of claim 2, wherein the device identifier generator comprises:

a calculator configured to calculate the received device identifier using a pre-defined value.

4. The system of claim 3, wherein the calculator comprises:

an adder configured to add the pre-defined value to the received device identifier to provide a new device identifier.

5. The system of claim 4, wherein the adder comprises:

adding circuitry configured to add 1 to the received device identifier.

6. The system of claim 4, wherein the device identifier receiver comprises:

a register configured to register the received device identifier in serial manner; and

a provider configured to output each of the registered device identifiers in parallel manner, thereby providing the device identifier for the calculation.

7. The system of claim 3, wherein the calculator comprises:

a subtracter configured to subtract the pre-defined value from the received device identifier to provide a new device identifier.

8. The system of claim 7, wherein the subtracter comprises:

subtracting circuitry configured to subtract 1 from the received device identifier.

9. The system of claim 8, wherein the controller comprises:

a provider configured to provide the initial device identifier to a first device in the serial interconnection configuration.

10. The system of claim 1, wherein the receiver comprises:

a processor configured to;

receive the device identifier from the last device; and

determine the number of devices in the serial interconnection configuration in response to the received device identifier.

11. The system of claim 1, wherein the receiver comprises:

a processor configured to;

receive the device identifier from the last device; and

determine a latency of the plurality of memory devices in the serial interconnection configuration in response to the received device identifier.

12. The system of claim 1, wherein the controller comprises:

a signal provider configured to provide the initial device identifier to the input connection of the first device of the serial interconnection configuration.

13. The system of claim 1, wherein the signal provider is configured to provide the control signal to the control input connection of the first device of the serial interconnection configuration.

14. The system of claim 1, wherein the controller comprises:

a signal receiver coupled to the output connection of the last device of the serial interconnection configuration, the signal receiver being configured to receive the device identifier from the output connection of the last device of the serial interconnection configuration.

15. A method for determining the characteristic of a plurality of memory devices in a serial interconnection configuration, each of the plurality of memory devices having a select input connection, an input connection, a output connection and an enable input connection, the select input connection of each device being coupled to receive a mode select signal, the input connection of each device being coupled to the output connection of a previous device, the enable input connection of each device being coupled to receive an enable signal from the previous device, the output connection of each device being coupled to the input connection of a subsequent device, the input connection of a first device of the serial interconnection configuration being coupled to receive an initial device identification from a controller, each of the plurality of memory devices including a producer, the method comprising:

setting the device in a device identification production mode in response to the received mode select signal;

by the producer of the device set in the device identification production mode, producing a device identifier in a response to an input device identifier received through its input connection in response to the enable signal, the device identifier produced by the producer of each device to be provided to the subsequent device through its output connection,

by the controller, receiving the device identifier from the last device in the serial interconnection configuration; and

determining, in the controller, the number of the plurality of memory devices in the serial interconnection configuration in response to the received device identifier.

16. The method of claim 15, further comprising:

providing a device identifier from a last device configured to determine the device related characteristic of the serial interconnection configuration.

17. The method of claim 16, wherein the producer comprises:

calculating the received device identifier using a pre-defined value in response to the control signal.

18. The method of claim 17, wherein the step of calculating comprises:

adding the pre-defined value to the received device identifier to provide a new device identifier.

19. The method of claim 17, wherein the step of determining comprises:

determining a latency of the plurality of memory devices in the serial interconnection configuration in response to the received device identifier.