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Scheduling events in a microprocessor using a plurality of delta time registers arranged as a sequence buffer and indicating a sequence position of the sequence buffer to process an event

  • US 8,984,323 B2
  • Filed: 09/28/2011
  • Issued: 03/17/2015
  • Est. Priority Date: 09/28/2011
  • Status: Active Grant
First Claim
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1. A microcontroller comprising:

  • a central processing unit (CPU);

    a plurality of peripherals; and

    a programmable scheduler unit comprising;

    a timer being clocked by an independent clock signal;

    a comparator coupled with a timer register of said timer and having an output generating an output signal;

    an event register coupled with said comparator;

    a plurality of delta time registers arranged as a sequence buffer;

    an arithmetic logic unit controlled by the output signal of the comparator and comprising first and second inputs and an output, wherein the first input is coupled with the timer register or the event register and the second input is coupled with the delta time register and the output is coupled with the event register; and

    an event logic unit receiving the output signal of the comparator and an output signal of said sequence buffer indicating a sequence position and controlling said arithmetic logic unit and event register and said sequence position is taken into consideration to process an event wherein said event logic unit is configured to generate a plurality of output signals.

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