Scheduling events in a microprocessor using a plurality of delta time registers arranged as a sequence buffer and indicating a sequence position of the sequence buffer to process an event

• US 8,984,323 B2
• Filed: 09/28/2011
• Issued: 03/17/2015
• Est. Priority Date: 09/28/2011
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Bowling, Stephen, Wojewoda, Igor
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): CASSITY, ROBERT A
• Application Number:
  US13/247,489
• Publication Number:
  US 20130080819A1
• Time in Patent Office: 1,266 Days
• Field of Search: 713/502
• US Class Current: 713/502
• CPC Class Codes: G06F 1/14 Time supervision arrangements, e.g. real time clock
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 15/7814 Specially adapted for real time processing, e.g. comprising hardware timers
• CPC Class Codes: G06F 15/7853 including a ROM
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A microcontroller has a central processing unit (CPU), a plurality of peripherals, and a programmable scheduler unit with: —a timer being clocked by an independent clock signal; —a comparator coupled with a timer register of said timer and having an output generating an output signal; —an event register coupled with said comparator; —a delta time register; and —an arithmetic logic unit controlled by the output signal of the comparator and with first and second inputs and an output, wherein the first input is coupled with the timer register or the event register and the second input is coupled with the delta time register and the output is coupled with the event register.

Claims

1. A microcontroller comprising:

a central processing unit (CPU);

a plurality of peripherals; and

a programmable scheduler unit comprising;

a timer being clocked by an independent clock signal;

a comparator coupled with a timer register of said timer and having an output generating an output signal;

an event register coupled with said comparator;

a plurality of delta time registers arranged as a sequence buffer;

an arithmetic logic unit controlled by the output signal of the comparator and comprising first and second inputs and an output, wherein the first input is coupled with the timer register or the event register and the second input is coupled with the delta time register and the output is coupled with the event register; and

an event logic unit receiving the output signal of the comparator and an output signal of said sequence buffer indicating a sequence position and controlling said arithmetic logic unit and event register and said sequence position is taken into consideration to process an event wherein said event logic unit is configured to generate a plurality of output signals.

2. The microcontroller according to claim 1, wherein when said comparator detects a match of said event register and said timer register, the arithmetic logic is controlled to perform an arithmetic function of data received at the first and second inputs and store a resulting value in said event register.

3. The microcontroller according to claim 1, wherein the sequence buffer is a circular sequence buffer which can be controlled to output contents of said delta time registers in a circular manner, in a single sequence, or a predetermined number of times.

4. The microcontroller according to claim 1, further comprising a data formatting unit coupled with at least one of said timer register and said delta time register, wherein said data formatting unit is operable to convert an absolute time value into a relative time value.

5. The microcontroller according to claim 1, further comprising a calibration unit coupled with a predefined number of bits of said timer register and operable to overwrite said predefined number of bits in said timer register.

6. The microcontroller according to claim 5, wherein said calibration unit overwrites said timer register bits periodically.

7. The microcontroller according to claim 1, wherein said clock select unit is operable to select between a plurality of clock signals generated by at least one peripheral timer unit.

8. The microcontroller according to claim 1, further comprising a clock select unit which is operable to select between internal and an external clock signals.

9. The microcontroller according to claim 1, wherein an output signal from said event logic unit is an interrupt signal.

10. The microcontroller according to claim 1, wherein an output signal from said event logic unit is a pulse signal having a predefined pulse width.

11. The microcontroller according to claim 1, wherein an output signal from said event logic unit is fed to a clock control unit to enable a predetermined clock source.

12. The microcontroller according to claim 1, further comprising an event distribution unit receiving said plurality of output signals from said event logic unit and generating output signals which are fed to at least one of said CPU and at least one peripheral device.

13. The microcontroller according to claim 12, further comprising a system power control unit coupled with said event distribution unit.

14. The microcontroller according to claim 1, wherein said microcontroller is battery operated.

15. The microcontroller according to claim 1, comprising a plurality of special function registers for programming said programmable scheduler unit.

16. The microcontroller according to claim 1, wherein the timer register and the event register are configured to store a UNIX time format.

17. The microcontroller according to claim 1, wherein the arithmetic logic unit is an adder.

18. A method of operating a microcontroller comprising a central processing unit (CPU),

a plurality of peripherals;

and

a programmable scheduler unit;

the method comprising;

programming a time value into timer register of a timer;

programming a plurality of predefined delta time values within a sequence buffer;

wherein if said event register matches said timer register, the scheduler unit automatically generates an event and adding the time value or a new time value to said event register,

further comprising processing said event to generate a plurality of output signals, wherein to process said event a sequence position of said sequence buffer is taken into consideration.

19. The method according to claim 18, wherein the step of programming the time value is performed by receiving a relative time or an absolute time and formatting said time to form said time value.

20. The method according to claim 18, wherein a matched event wakes the CPU from a Sleep mode.

21. The method according to claim 18, wherein a matched event wakes a peripheral from a Sleep mode for a predetermined time while the CPU remains in a Sleep mode.

22. The method according to claim 21, wherein during the predetermined time, the peripheral generates a signal to wake said CPU.

23. The method according to claim 18, wherein the sequence buffer is a circular sequence buffer.

24. The method according to claim 18, wherein the sequence buffer is operable to be controlled t output the time values in a circular manner, in a single sequence, or predetermined number of times.

25. The method according to claim 18, further the timer and event registers store a value in UNIX time format.

26. The method according to claim 18, further comprising periodically calibrating said timer register by means of a calibration unit.

27. The method according to claim 18, wherein docking said timer register is selected between internal and an external clock signals.

28. The method according to claim 18, wherein an output signal from said plurality of output signals is an interrupt signal.

29. The method according to claim 18, wherein an output signal from said plurality of output signals is a pulse signal having a predefined pulse width plurality of output signals is fed to a system power control unit.

30. The method according to claim 27, wherein generating said event comprises distributing a plurality of output signals to at least one of:

said CPU and at least one peripheral device.

31. The method according to claim 30, wherein at least one signal of said plurality of output signals is fed to a system power control unit.

32. The method according to claim 30, wherein at least one signal of said plurality of output signals is fed to a clock control unit to enable a predetermined clock source.