Data transfer across power domains

• US 8,984,463 B2
• Filed: 03/11/2013
• Issued: 03/17/2015
• Est. Priority Date: 11/28/2012
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Xie, Jing, Du, Yang
• Primary Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US13/792,592
• Publication Number:
  US 20140146630A1
• Time in Patent Office: 736 Days
• Field of Search: None
• US Class Current: 716/120
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/396 Clock trees
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/0008 Arrangements for reducing power consumption
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The disclosed embodiments comprise a multi-stage circuit operating across different power domains. The multi-stage circuit may be implemented as a master-slave flip-flop circuit integrated with a level shifter that transfers data across different power domains. The master and slave stages of the flip-flop may be split across two tiers of a 3D IC and may include (i) a level shifter across different power domain integrated within the flip-flop circuit, (ii) reduced one-state writing delays by a self-induced power collapsing technique, (iii) splitting flip-flop power supplies in different tiers using monolithic 3D IC technology, and (iv) cross power domain data transfer between 3D IC tiers.

Claims

1. A multi-tier integrated circuit comprising:

a multi-stage circuit configuration comprising a first stage operating in power domain A and a second stage operating in power domain B;

said first stage comprising first means for storing data;

said second stage comprising means for level shifting and storing data;

a first tier;

a second tier;

said first tier comprising said first stage and means for providing power to said first stage; and

said second tier comprising said second stage and means for providing power to said second stage.

2. The integrated circuit of claim 1 wherein:

said means for providing power to said first stage comprises a first power rail; and

said means for providing power to said second stage comprises a second power rail.

3. The integrated circuit of claim 2 further comprising means for transporting data between said first stage and said second stage.

4. The integrated circuit of claim 3 wherein said means for transporting data comprises a network of vias.

5. The integrated circuit of claim 4 wherein said network of vias comprises monolithic inter-tier vias.

6. A multi-stage circuit configuration comprising:

a first stage operating in power domain A;

said first stage comprising first means for storing data;

a second stage operating in power domain B;

said second stage comprising means for isolating said first stage operating in power domain A from said second stage operating in power domain B;

said second stage further comprising means for level shifting and storing data in power domain B;

wherein said means for level shifting and storing further comprises means for enhancing writing data to said means for level shifting and storing;

a first tier and a second tier;

said first tier comprising said first stage and means for providing power to said first stage; and

said second tier comprising said second stage and means for providing power to said second stage.

7. The configuration of claim 6 wherein:

said means for providing power to said first stage comprises a first power rail; and

said means for providing power to said second stage comprises a second power rail.

8. The configuration of claim 7 further comprising means for transporting data between said first stage and said second stage.

9. The configuration of claim 8 wherein said means for transporting data comprises a network of vias.

10. The configuration of claim 9 wherein said network of vias comprises monolithic inter-tier vias.

11. The configuration of claim 6 wherein:

said means for storing data comprises a master flip-flop;

said means for level shifting and storing data comprises a slave flip-flop and level shifter circuitry.

12. The configuration of claim 11 wherein said slave flip-flop and level shifter comprises a plurality of SRAM transistors.

13. The configuration of claim 11 wherein said means for level shifting and storing data comprises less than about 70% of a total circuitry area of the multi-stage circuit configuration.

14. The configuration of claim 6 wherein said means for isolating comprises common source n-channel MOSFETs.

15. The configuration of claim 6 wherein said means for enhancing comprises an always on p-channel MOSFET header.

16. A multi-stage circuit configuration comprising:

a first stage operating in power domain A, the first stage comprising a storage circuit;

a second stage operating in power domain B;

said second stage comprising level shifter storage circuitry and a self-induced power collapsing circuit coupled to the level shifter storage circuitry; and

said second stage further comprising isolation circuitry to receive an input signal from the storage circuit.

17. The configuration of claim 16 wherein said level shifter storage circuitry further comprises write enhancement functionality.

18. The configuration of claim 17 further comprising:

a first tier and a second tier;

said first tier comprising said first stage and a first stage power rail; and

said second tier comprising said second stage and a second stage power rail.

19. The configuration of claim 18 further comprising a network of vias for transmitting data between said first stage and said second stage.

20. The configuration of claim 19 wherein said network of vias comprises monolithic inter-tier vias.

21. The configuration of claim 17 wherein:

said first stage comprises a first flip-flop circuit; and

said level shifter storage circuitry comprises a second flip flop circuit.

22. The configuration of claim 17 wherein said write enhancement improves the efficiency of writing the data to said level shifter storage circuitry.

23. The configuration of claim 22 wherein said write enhancement comprises a p-channel MOSFET.

24. The configuration of claim 16 wherein:

said first flip-flop circuit comprises a master flip-flop configuration; and

said second flip-flop circuit comprises a slave flip-flop configuration.

25. The configuration of claim 24 wherein said slave flip-flop configuration comprises an SRAM cell.

26. The configuration of claim 16 wherein said isolation circuitry limits cross-talk between said first stage operating in power domain A and said level shifter storage circuitry operating in power domain B.

27. The configuration of claim 26 wherein said isolation circuitry comprises differential n-channel MOSFETs.

28. A computer-readable storage medium having instructions stored to cause a processor to perform a method of designing a multi-stage circuit, the method comprising:

designing a first stage circuit operating in power domain A;

designing a second stage circuit operating in power domain B;

incorporating level shifter storage circuitry into said second stage circuit, wherein said level shifter storage circuit shifts data received at power domain A to power domain B, and writes said shifted data to said level shifter storage;

locating said first stage circuit and a first stage power rail on a first tier of a multi-tier configuration; and

locating said second stage circuit and second stage power rail on a second tier of said multi-tier configuration.

29. A computer-readable storage medium having instructions stored to cause a processor to perform a method of designing a multi-stage circuit, the method comprising:

designing a first stage storage circuit operating in power domain A;

designing a second stage circuitry operating in power domain B;

incorporating level shifter storage circuitry into said second stage circuitry, wherein said level shifter storage circuitry shifts received data from power domain A to power domain B, and writes said shifted data to said level shifter storage circuitry;

incorporating write enhancement into said level shifter storage circuitry, wherein said write enhancement improves an efficiency of writing said shifted data to said level shifter storage circuitry;

reducing a size and a power consumption of said level shifter storage circuitry;

incorporating isolation circuitry into said second storage circuitry, wherein said isolation circuitry limits cross talk between said first stage storage circuitry operating in power domain A and said second stage circuitry operating in power domain B;

further adjusting said design or reducing said size or power consumption of said level shifter storage circuitry, if necessary; and

adjusting said design, size and/or power consumption of said isolation circuitry, if necessary.

30. The computer-readable medium of claim 29, the method further comprising the steps of:

evaluating whether said size, power consumption and/or writing efficiency of said second stage circuitry are optimized;

further adjusting said design or reducing said size or power consumption of said level shifter storage circuitry, if necessary; and

adjusting said design, size and/or power consumption of said isolation circuitry, if necessary.

31. The computer-readable medium of claim 30, the method further comprising the steps of;

locating said first stage storage circuitry and a first stage power rail on a first tier of a multi-tier configuration; and

locating said second storage circuit and a second stage power rail on a second tier of said multi-tier configuration.

32. The computer-readable medium of claim 29 wherein:

said first stage comprises a first flip-flop circuit; and

said level shifter storage circuitry comprises a second flip flop circuit.

33. The computer-readable medium of claim 32 wherein:

said first flip-flop circuit comprises a master flip-flop configuration; and

said second flip-flop circuit comprises a slave flip-flop configuration.

34. The computer-readable medium of claim 33 wherein said slave flip-flop configuration comprises an SRAM cell.

35. The computer-readable medium of claim 32 wherein said isolation circuitry limits cross-talk between said first stage operating in power domain A and said level shifter storage circuitry operating in power domain B.

36. The computer-readable medium of claim 35 wherein said isolation circuitry comprises differential n-channel MOSFETs.

37. The computer-readable medium of claim 29 wherein said write enhancement improves the efficiency of writing the data to said level shifter storage circuitry.

38. The computer-readable medium of claim 37 wherein said write enhancement comprises a p-channel MOSFET.