Methods, systems, and articles of manufacture for automatically assigning track patterns to regions for physical implementation of an electronic design

• US 8,984,465 B1
• Filed: 06/28/2013
• Issued: 03/17/2015
• Est. Priority Date: 06/28/2013
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Salowe, Jeffrey S.
• Primary Examiner(s): Parihar, Suchin
• Application Number:
  US13/931,707
• Time in Patent Office: 627 Days
• Field of Search: 716/100, 716/122
• US Class Current: 716/122
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

Various aspects described herein identify an area in an electronic design, identify a set of track patterns or track pattern groups for the area based on a set of criteria, and iteratively implement the electronic design in the area using at least some of the set of track patterns. These aspects may dynamically or iteratively update the assignment of one or more track patterns to the region based at least in part upon the implementation of the electronic design in the area or one or more attributes of one or more other areas on the same layer as the current layer of interest or on one or more different layers.

Claims

1. A computer implemented method for automatically assigning track patterns to regions for physical implementation of an electronic design, comprising:

using a computing system having at least one processor or at least one processor core to perform a process, the process comprising;

identifying a set of one or more track patterns that match a circuit feature in an area of an electronic design, wherein a track pattern in the set includes multiple tracks, each of which has zero width and is used for implementing the area of the electronic design;

implementing the circuit feature in the area of the electronic design by using one or more tracks identified from at least a part of the set of track patterns; and

updating assignment of one or more track patterns to the area.

2. The computer implemented method of claim 1, wherein the act of updating the assignment is based at least in part upon a result of implementing multiple circuit features in the area in an dynamic or iterative manner.

3. The computer implemented method of claim 1, the process further comprising:

making all track patterns available for the region; and

determining whether or not one or more attributes of a track pattern in the all track patterns match one or more corresponding attributes of the circuit feature to be implemented in the area.

4. The computer implemented method of claim 1, the process further comprising at least one of:

determining whether there is an existing circuit feature in the area;

determining whether there is an existing circuit feature in an adjacent area that is adjacent to the area; and

determining whether there is an existing circuit feature on an adjacent layer that is adjacent to a layer on which the area resides.

5. The computer implemented method of claim 4, the process further comprising:

determining or identifying one or more characteristics of the existing circuit feature; and

adjusting the assignment of one or more track patterns to the area based at least in part upon the one or more characteristics.

6. The computer implemented method of claim 4, the process further comprising:

tessellating the area into multiple, smaller sub-areas; and

accommodating the existing circuit feature by using at least one sub-area of the multiple, smaller sub-areas.

7. The computer implemented method of claim 1, the act of identifying the set of track patterns that match the circuit feature further comprising:

identifying one or more circuit feature attributes associated with the circuit feature;

identifying one or more track pattern attributes that correspond respectively to the one or more circuit feature attributes; and

determining if the one or more circuit feature attributes are compatible with the one or more circuit track pattern attributes, wherein

a matching track pattern is determined to match the circuit feature if at least one of the one or more circuit track pattern attributes is compatible with a corresponding circuit feature attribute of the circuit feature.

8. The computer implemented method of claim 1, the act of updating the assignment of the one or more track patterns to the area comprising:

identifying a count for a first track pattern of the one or more track patterns;

determining whether implementing the circuit feature in the area affects the count; and

modifying the count based at least in part upon a result of determining whether implementing the circuit feature in the area affects the count.

9. The computer implemented method of claim 1, the act of updating the assignment of the one or more track patterns to the area comprising:

identifying historical data from one or more similar electronic designs based at least in part upon contextual information of the area.

10. The computer implemented method of claim 9, the act of updating the assignment of the one or more track patterns to the area comprising:

identifying a context in which the area is situated in the electronic design;

identifying one or more areas situated within identical or similar context as the area is in the context from the one or more similar electronic designs;

identifying one or more track pattern assignments from the one or more similar electronic designs; and

modifying the set of track patterns based at least in part upon the one or more track pattern assignments.

11. The computer implemented method of claim 1, the act of implementing the circuit feature comprising:

identifying the one or more tracks from the part of the set of track patterns; and

using the one or more tracks to implement the circuit feature in the area.

12. The computer implemented method of claim 1, the process further comprising:

identifying a single track pattern from the set of track patterns; and

locking the assignment by associating only the single track pattern with the region.

13. The computer implemented method of claim 1, the process further comprising:

maintaining a tessellation structure for at least the area, wherein the tessellation structure includes information about the region and the assignment.

14. The computer implemented method of claim 1, the process further comprising:

determining a requirement that requires a total number of circuit features equal a count associated with a track pattern;

relaxing the requirement to allow for an error; and

leveraging the error in implementing a part of the area or the electronic design.

15. A system for automatically assigning track patterns to regions for physical implementation of an electronic design, comprising:

a computing system having at least one processor or at least one processor core that is to;

identify a set of one or more track patterns that match a circuit feature in an area of an electronic design, wherein a track pattern in the set includes multiple tracks, each of which has zero width and is used for implementing the area of the electronic design;

implement the circuit feature in the area of the electronic design by using one or more tracks identified from at least a part of the set of track patterns; and

update assignment of one or more track patterns to the area.

16. The system of claim 15, in which the at least one processor or at least one processor core is further to:

execute one or more sets of instructions of multiple sets of instructions to implement the physical electronic design with the area-bounded tracks, wherein

a first set of instructions of the multiple sets of instructions comprises a first sequence of instructions which, when executed by the at least one processor, causes the at least one processor to;

make all track patterns available for the region; and

determine whether or not one or more attributes of a track pattern in the all track patterns match one or more corresponding attributes of the circuit feature to be implemented in the area;

a second set of instructions of the multiple sets of instructions comprises a first sequence of instructions which, when executed by the at least one processor, causes the at least one processor to;

determine whether there is an existing circuit feature in the area;

determine whether there is an existing circuit feature in an adjacent area that is adjacent to the area;

or

determine whether there is an existing circuit feature on an adjacent layer that is adjacent to a layer on which the area resides; and

a third set of instructions of the multiple sets of instructions comprises a first sequence of instructions which, when executed by the at least one processor, causes the at least one processor to;

determine or identify one or more characteristics of the existing circuit feature;

adjust the assignment of one or more track patterns to the area based at least in part upon the one or more characteristics;

tessellate the area into multiple, smaller sub-areas; and

accommodate the existing circuit feature by using at least one sub-area of the multiple, smaller sub-areas.

17. The system of claim 15, in which the at least one processor or at least one processor core that is to identify the set of track patterns that match the circuit feature is further to:

identify one or more circuit feature attributes associated with the circuit feature;

identify one or more track pattern attributes that correspond respectively to the one or more circuit feature attributes; and

determine if the one or more circuit feature attributes are compatible with the one or more circuit track pattern attributes, wherein

a matching track pattern is determined to match the circuit feature if at least one of the one or more circuit track pattern attributes is compatible with a corresponding circuit feature attribute of the circuit feature.

18. The system of claim 15, in which the at least one processor or at least one processor core that is further to update the assignment of the one or more track patterns to the area is further to:

execute one or more sets of instructions of multiple sets of instructions to implement the physical electronic design with the area-bounded tracks, wherein

a first set of instructions of the multiple sets of instructions comprises a first sequence of instructions which, when executed by the at least one processor, causes the at least one processor to;

identify a count for a first track pattern of the one or more track patterns;

determine whether implementing the circuit feature in the area affects the count;

modify the count based at least in part upon a result of determining whether implementing the circuit feature in the area affects the count; and

identify historical data from one or more similar electronic designs based at least in part upon contextual information of the area; and

a second set of instructions of the multiple sets of instructions comprises a first sequence of instructions which, when executed by the at least one processor, causes the at least one processor to;

identify a context in which the area is situated in the electronic design;

identify one or more areas situated within identical or similar context as the area is in the context from the one or more similar electronic designs;

identify one or more track pattern assignments from the one or more similar electronic designs; and

modify the set of track patterns based at least in part upon the one or more track pattern assignments.

19. The system of claim 15, in which the at least one processor or at least one processor core is further to implement the circuit feature is further to:

identify the one or more tracks from the part of the set of track patterns; and

use the one or more tracks to implement the circuit feature in the area.

20. The system of claim 15, in which the at least one processor or at least one processor core is further to:

execute one or more sets of instructions of multiple sets of instructions to implement the physical electronic design with the area-bounded tracks, wherein

a first set of instructions of the multiple sets of instructions comprises a first sequence of instructions which, when executed by the at least one processor, causes the at least one processor to;

identify a single track pattern from the set of track patterns; and

lock the assignment by associating only the single track pattern with the region; and

a second set of instructions of the multiple sets of instructions comprises a first sequence of instructions which, when executed by the at least one processor, causes the at least one processor to;

determine a requirement that requires a total number of circuit features equal a count associated with a track pattern;

relax the requirement to allow for an error; and

leverage the error in implementing a part of the area or the electronic design.

21. An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core executing one or more threads, causes the at least one processor or the at least one processor core to perform a method for automatically assigning track patterns to regions for physical implementation of an electronic design, the method comprising:

using at least one processor or at least one processor core to perform a process the process comprising;

identifying a set of one or more track patterns that match a circuit feature in an area of an electronic design, wherein a track pattern in the set includes multiple tracks, each of which has zero width and is used for implementing the area of the electronic design;

implementing the circuit feature in the area of the electronic design by using one or more tracks identified from at least a part of the set of track patterns; and

updating assignment of one or more track patterns to the area.

22. The article of manufacture of claim 21, the process further comprising:

one or more sub-processes of multiple sub-processes, wherein

a first sub-process of the multiple sub-processes comprises;

making all track patterns available for the region; and

determining whether or not one or more attributes of a track pattern in the all track patterns match one or more corresponding attributes of the circuit feature to be implemented in the area; and

a second sub-process of the multiple sub-processes comprises;

determining whether there is an existing circuit feature in the area;

determining whether there is an existing circuit feature in an adjacent area that is adjacent to the area; and

determining whether there is an existing circuit feature on an adjacent layer that is adjacent to a layer on which the area resides.

23. The article of manufacture of claim 22, the process further comprising:

determining or identifying one or more characteristics of the existing circuit feature;

adjusting the assignment of one or more track patterns to the area based at least in part upon the one or more characteristics;

tessellating the area into multiple, smaller sub-areas; and

accommodating the existing circuit feature by using at least one sub-area of the multiple, smaller sub-areas.

24. The article of manufacture of claim 21, the act of identifying the set of track patterns that match the circuit feature further comprising:

identifying one or more circuit feature attributes associated with the circuit feature;

identifying one or more track pattern attributes that correspond respectively to the one or more circuit feature attributes; and

determining if the one or more circuit feature attributes are compatible with the one or more circuit track pattern attributes, wherein

a matching track pattern is determined to match the circuit feature if at least one of the one or more circuit track pattern attributes is compatible with a corresponding circuit feature attribute of the circuit feature.

25. The article of manufacture of claim 21, the act of updating the assignment of the one or more track patterns to the area comprising one or more sub-processes of multiple sub-processes, wherein:

a first sub-process of the multiple sub-processes comprises;

identifying a count for a first track pattern of the one or more track patterns;

determining whether implementing the circuit feature in the area affects the count; and

modifying the count based at least in part upon a result of determining whether implementing the circuit feature in the area affects the count; and

a second sub-process of the multiple sub-processes comprises;

identifying historical data from one or more similar electronic designs based at least in part upon contextual information of the area;

identifying a context in which the area is situated in the electronic design;

identifying one or more areas situated within identical or similar context as the area is in the context from the one or more similar electronic designs;

identifying one or more track pattern assignments from the one or more similar electronic designs; and

modifying the set of track patterns based at least in part upon the one or more track pattern assignments.

26. The article of manufacture of claim 21, the act of implementing the circuit feature comprising:

identifying the one or more tracks from the part of the set of track patterns; and

using the one or more tracks to implement the circuit feature in the area.

27. The article of manufacture of claim 25, the process further comprising:

one or more sub-processes of multiple sub-processes, wherein

a first sub-process of the multiple sub-processes comprises;

identifying a single track pattern from the set of track patterns; and

locking the assignment by associating only the single track pattern with the region; and

a second sub-process of the multiple sub-processes comprises;

determining a requirement that requires a total number of circuit features equal a count associated with a track pattern;

relaxing the requirement to allow for an error; and

leveraging the error in implementing a part of the area or the electronic design.