Semiconductor light-emitting device and method for manufacturing same

• US 8,987,020 B2
• Filed: 09/12/2012
• Issued: 03/24/2015
• Est. Priority Date: 11/19/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kojima, Akihiro, Sugizaki, Yoshiaki
• Primary Examiner(s): YEUNG LOPEZ, FEIFEI
• Application Number:
  US13/611,393
• Publication Number:
  US 20130034921A1
• Time in Patent Office: 923 Days
• Field of Search: None
• US Class Current: 438/26
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2933/0041 relating to wavelength conversion elements
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/36 characterised by the electrodes
• CPC Class Codes: H01L 33/38 with a particular shape
• CPC Class Codes: H01L 33/382 the electrode extending partially in or entirely through the semiconductor body
• CPC Class Codes: H01L 33/385 the electrode extending at least partially onto a side surface of the semiconductor body
• CPC Class Codes: H01L 33/387 with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/486 adapted for surface mounting
• CPC Class Codes: H01L 33/50 : Wavelength conversion elements
• CPC Class Codes: H01L 33/507 : the elements being in intimate contact with parts other than the semiconductor body or integrated with parts other than the semiconductor body
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A method for manufacturing a semiconductor light-emitting device includes forming a multilayer body including a first semiconductor layer having a first major surface and a second major surface which is an opposite side from the first major surface, a second semiconductor layer including a light-emitting layer laminated on the second major surface of the first semiconductor layer, and electrodes formed on the second major surface of the first semiconductor layer and on a surface of the second semiconductor layer on an opposite side from the first semiconductor layer. The method includes forming a groove through the first semiconductor layer. The method includes forming a phosphor layer on the first major surface and on a side surface of the first semiconductor layer in the groove.

Claims

1. A method for manufacturing a semiconductor light-emitting device, comprising:

forming a multilayer body including a first semiconductor layer having a first major surface and a second major surface which is an opposite side from the first major surface, a second semiconductor layer including a light-emitting layer laminated on the second major surface of the first semiconductor layer, and electrodes formed on the second major surface of the first semiconductor layer and on a surface of the second semiconductor layer on an opposite side from the first semiconductor layer;

forming a groove through the first semiconductor layer;

forming a phosphor layer on the first major surface and on a side surface of the first semiconductor layer in the groove; and

forming an insulating layer on the second major surface of the first semiconductor layer and on the electrodes, the insulating layer having a first surface above a lower surface of the second semiconductor layer and a second surface which is an opposite side from the first surface, wherein

the first semiconductor layer and the second semiconductor layer are formed on a substrate,

the substrate is removed after the forming the insulating layer,

the groove is formed after the removing the substrate.

2. The method of claim 1, wherein the forming the phosphor layer includes:

applying a liquid resin mixed with phosphor particles onto the groove and the first major surface;

and curing the applied resin.

3. The method of claim 1, wherein the phosphor layer is conformally formed along the first major surface and the side surface of the first semiconductor layer.

4. The method of claim 1, wherein the groove is reached to the first surface of the insulating layer through the first semiconductor layer.

5. The method of claim 1, wherein the phosphor layer is continuously formed on a step portion between the first surface of the insulating layer and the first major surface of the first semiconductor layer.

6. The method of claim 1, wherein the phosphor layer is formed on the first surface of the insulating layer and is not formed on a side surface of the insulating layer.

7. The method of claim 1, further comprising:

after the forming the phosphor layer, performing singulation by dicing at the groove.

8. The method of claim 1, further comprising:

after the forming the phosphor layer, performing singulation by dicing at a portion outside the groove.

9. A method for manufacturing a semiconductor light-emitting device, comprising:

forming a multilayer body including a first semiconductor layer having a first major surface and a second major surface which is an opposite side from the first major surface, a second semiconductor layer including a light-emitting layer laminated on the second major surface of the first semiconductor layer, and electrodes formed on the second major surface of the first semiconductor layer and on a surface of the second semiconductor layer on an opposite side from the first semiconductor layer;

forming a groove through the first semiconductor layer;

forming a phosphor layer on the first major surface and on a side surface of the first semiconductor layer in the groove; and

forming an insulating layer on the second major surface of the first semiconductor layer and on the electrodes, the insulating layer having a first surface above a lower surface of the second semiconductor layer and a second surface which is an opposite side from the first surface, wherein

the groove is reached to the first surface of the insulating layer through the first semiconductor layer.

10. A method for manufacturing a semiconductor light-emitting device, comprising:

forming a multilayer body including a first semiconductor layer having a first major surface and a second major surface which is an opposite side from the first major surface, a second semiconductor layer including a light-emitting layer laminated on the second major surface of the first semiconductor layer, and electrodes formed on the second major surface of the first semiconductor layer and on a surface of the second semiconductor layer on an opposite side from the first semiconductor layer;

forming a groove through the first semiconductor layer;

forming a phosphor layer on the first major surface and on a side surface of the first semiconductor layer in the groove; and

forming an insulating layer on the second major surface of the first semiconductor layer and on the electrodes, the insulating layer having a first surface above a lower surface of the second semiconductor layer and a second surface which is an opposite side from the first surface, wherein

the phosphor layer is formed on the first surface of the insulating layer and is not formed on a side surface of the insulating layer.