Method of making a semiconductor device using sacrificial fins

• US 8,987,082 B2
• Filed: 05/31/2013
• Issued: 03/24/2015
• Est. Priority Date: 05/31/2013
• Status: Active Grant

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Loubet, Nicolas, Khare, Prasanna
• Primary Examiner(s): Patel, Reema
• Application Number:
  US13/906,758
• Publication Number:
  US 20140357029A1
• Time in Patent Office: 662 Days
• Field of Search: 438/212, 438/424, 438/156, 438/268
• US Class Current: 438/212
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

A method of making a semiconductor device includes forming a sacrificial layer above a semiconductor layer. Portions of the sacrificial layer are selectively removed to define a first set of spaced apart sacrificial fins over a first region of the semiconductor layer, and a second set of spaced apart sacrificial fins over a second region of the semiconductor layer. An isolation trench is formed in the semiconductor layer between the first and second regions. The isolation trench and spaces are filled with a dielectric material. The first and second sets of sacrificial fins are removed to define respective first and second sets of fin openings. The first set of fin openings is filled to define a first set of semiconductor fins for a first conductivity-type transistor, and the second set of fin openings is filled to define a second set of semiconductor fins for a second conductivity-type transistor.

Claims

1. A method of making a semiconductor device comprising:

forming a sacrificial layer above a semiconductor layer, the semiconductor layer comprising a first region for a first conductivity-type transistor and a second region laterally adjacent the first region for a second conductivity-type transistor;

selectively removing portions of the sacrificial layer to define a first set of spaced apart sacrificial fins over the first region, and a second set of spaced apart sacrificial fins over the second region;

forming an isolation trench in the semiconductor layer between the first and second regions;

filling, with a dielectric material, the isolation trench and spaces between adjacent ones of the first and second sets of spaced apart sacrificial fins and annealing to densify the dielectric material;

removing the first and second sets of sacrificial fins to define respective first and second sets of fin openings; and

filling the first set of fin openings to define a first set of semiconductor fins for the first conductivity-type transistor, and filling the second set of fin openings to define a second set of semiconductor fins for the second conductivity-type transistor.

2. The method according to claim 1 wherein filling, with the dielectric material, the isolation trench and spaces between adjacent ones of the first and second sets of spaced apart fin openings has a higher thermal budget than a thermal budget for filling the first and second sets of fin openings.

3. The method according to claim 1 wherein removing the first and second sets of sacrificial fins and filling the first and second sets of fin openings comprises:

masking the second set of sacrificial fins while removing the first set of sacrificial fins and filling the first set of fin openings; and

masking the first set of semiconductor fins while removing the second set of sacrificial fins and filling the second set of fin openings.

4. The method according to claim 1 further comprising forming a dielectric layer between the semiconductor layer and the sacrificial layer.

5. The method according to claim 4 further comprising selectively removing underlying portions of the dielectric layer aligned with the first and second sets of sacrificial fins when removing the first and second sets of sacrificial fins to thereby expose respective underlying surfaces of the first and second regions.

6. The method according to claim 1 wherein filling the first set of fin openings comprises epitaxially growing a silicon-germanium bottom region and a silicon top region thereover;

and wherein filling the second set of fin openings comprises epitaxially growing a silicon bottom region and a silicon-germanium region thereover.

7. The method according to claim 1 wherein the semiconductor layer comprises silicon;

and wherein the sacrificial layer comprises polysilicon.

8. The method according to claim 1 wherein the dielectric material comprises an oxide.

9. A method of making a semiconductor device comprising:

forming a sacrificial layer above a semiconductor layer, the semiconductor layer comprising a first region for a first conductivity-type transistor and a second region laterally adjacent the first region for a second conductivity-type transistor;

selectively removing portions of the sacrificial layer to define a first set of spaced apart sacrificial fins over the first region, and a second set of spaced apart sacrificial fins over the second region;

forming an isolation trench in the semiconductor layer between the first and second regions;

filling, with a dielectric material, the isolation trench and spaces between adjacent ones of the first and second sets of spaced apart sacrificial fins and annealing to densify the dielectric material;

masking the second set of sacrificial fins while removing the first set of sacrificial fins, and filling the first set of fin openings to define a set of first semiconductor fins for the first conductivity-type transistor; and

masking the first set of semiconductor fins while removing the second set of sacrificial fins, and filling the second set of fin openings to define a second set of semiconductor fins for the second conductivity-type transistor.

10. The method according to claim 9 wherein filling, with the dielectric material, the isolation trench and spaces between adjacent ones of the first second sets of spaced apart fin openings has a higher thermal budget than a thermal budget for filling the first and second sets of fin openings.

11. The method according to claim 9 further comprising forming a dielectric layer between the semiconductor layer and the sacrificial layer.

12. The method according to claim 11 further comprising selectively removing underlying portions of the dielectric layer aligned with the first set of sacrificial fins when removing the first set of sacrificial fins to thereby expose underlying surfaces of the first region.

13. The method according to claim 11 further comprising selectively removing underlying portions of the dielectric layer aligned with the second set of sacrificial fins when removing the second set of sacrificial fins to thereby expose underlying surfaces of the second region.

14. The method according to claim 9 wherein filling the first set of fin openings comprises epitaxially growing a silicon-germanium bottom region and a silicon top region thereover.

15. The method according to claim 9 wherein filling the second set of fin openings comprises epitaxially growing a silicon bottom region and a silicon-germanium region thereover.

16. The method according to claim 9 wherein the semiconductor layer comprises silicon;

and wherein the sacrificial layer comprises polysilicon.

17. The method according to claim 9 wherein the dielectric material comprises an oxide.

18. A method of making a semiconductor device comprising:

forming a polysilicon sacrificial layer above a silicon layer, the silicon layer comprising a first region for a first conductivity-type transistor and a second region laterally adjacent the first region for a second conductivity-type transistor;

selectively removing portions of the polysilicon sacrificial layer to define a first set of spaced apart polysilicon sacrificial fins over the first region and a second set of spaced apart polysilicon sacrificial fins over the second region;

forming an isolation trench in the semiconductor layer between the first and second regions;

filling, with an oxide material, the isolation trench and spaces between adjacent ones of the first and second sets of spaced apart sacrificial fins and annealing to densify the oxide material;

removing the first and second sets of polysilicon sacrificial fins to define respective first and second sets of fin openings; and

filling the first set of fin openings to define a first set of semiconductor fins for the first conductivity-type transistor, and filling the second set of fin openings to define a second set of semiconductor fins for the second conductivity-type transistor.

19. The method according to claim 18 wherein filling, with the oxide material, the isolation trench and spaces between adjacent ones of the first and second sets of spaced apart fin openings has a higher thermal budget than a thermal budget for filling the first and second sets of fin openings.

20. The method according to claim 18 wherein removing the first and second sets of polysilicon sacrificial fins and filling the first and second sets of fin openings comprises:

masking the second set of polysilicon sacrificial fins while removing the first set of polysilicon sacrificial fins and filling the first set of fin openings; and

masking the first set of semiconductor fins while removing the second set of polysilicon sacrificial fins and filling the second set of fin openings.

21. The method according to claim 18 further comprising forming a dielectric layer between the semiconductor layer and the sacrificial layer.

22. The method according to claim 21 further comprising selectively removing underlying portions of the dielectric layer aligned with the first and second sets of polysilicon sacrificial fins when removing the first and second sets of polysilicon sacrificial fins to thereby expose respective underlying surfaces of the first and second regions.

23. The method according to claim 18 wherein filling the first set of fin openings comprises epitaxially growing a silicon-germanium bottom region and a silicon top region thereover;

and wherein filling the second set of fin openings comprises epitaxially growing a silicon bottom region and a silicon-germanium region thereover.