FinFETs and methods for forming the same

• US 8,987,791 B2
• Filed: 02/27/2013
• Issued: 03/24/2015
• Est. Priority Date: 02/27/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Yu-Lien, Fan, Chun-Hsiang, Li, Yung-Ta, Tsai, Ming-Huan, Wann, Clement Hsingjen, Liu, Chi-Wen, Perng, Tsu-Hsiu, Liu, Chi-Kang
• Primary Examiner(s): Tran, Minh-Loan
• Assistant Examiner(s): Erdem, Fazli
• Application Number:
  US13/779,356
• Publication Number:
  US 20140239354A1
• Time in Patent Office: 755 Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3247 for altering the shape, e.g. smoothing the surface
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/34 the imperfections being on the surface
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

A finFET and methods for forming a finFET are disclosed. A structure comprises a substrate, a fin, a gate dielectric, and a gate electrode. The substrate comprises the fin. The fin has a major surface portion of a sidewall, and the major surface portion comprises at least one lattice shift. The at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the sidewall. The gate electrode is on the gate dielectric.

Claims

1. A structure comprising:

a substrate comprising a fin, the fin having a first surface portion of a sidewall and a second surface portion of the sidewall, the first surface portion being at and extending below a top surface edge of an isolation region in the substrate, the first surface portion adjoining the isolation region, the first surface portion being in a plane, the second surface portion comprising at least one lattice shift away from the plane;

a gate dielectric on the second surface portion of the sidewall, the gate dielectric contacting the sidewall on at least a portion of the at least one lattice shift; and

a gate electrode on the gate dielectric.

2. The structure of claim 1, wherein the second surface portion comprises a plurality of lattice shifts, the lattice shifts comprising a plurality of inward shifts away from the plane and toward a center of the fin.

3. The structure of claim 1, wherein the second surface portion comprises a plurality of lattice shifts, the lattice shifts comprising a plurality of outward shifts away from the plane and away from a center of the fin.

4. The structure of claim 1, wherein the second surface portion comprises a plurality of lattice shifts, the lattice shifts comprising a combination of inward shifts away from the plane and toward a center of the fin and outward shifts away from the plane and toward a center of the fin.

5. The structure of claim 1, wherein the at least one lattice shift comprises a lattice shift of at least two lattice spacings.

6. The structure of claim 1, wherein the at least one lattice shift comprises a plurality of lattice shifts, respective distances between neighboring lattice shifts being between 2 atoms and 20 atoms along a direction perpendicular to the lattice shifts.

12. The structure of claim 1, wherein the second surface portion of the sidewall is a channel region, the channel region comprising the at least one lattice shift.

7. A structure comprising:

a fin on a substrate, the fin having a first surface portion of a sidewall of the fin and a second surface portion of the sidewall of the fin, the substrate comprising an isolation region adjoining the first surface portion, the first surface portion being in a sidewall plane;

a gate dielectric adjoining atoms in multiple parallel planes on the second surface portion of the sidewall of the fin, the multiple parallel planes being perpendicular to a major surface of the substrate, neighboring pairs of the multiple parallel planes being separated by at least one lattice constant, a first group of the atoms being in a first one of the multiple parallel planes, a second group of the atoms being in a second one of the multiple parallel planes, at least some of the atoms not being in the sidewall plane; and

a gate electrode on the gate dielectric.

8. The structure of claim 7, wherein the second group is more distal from the major surface of the substrate than the first group, the first one of the multiple parallel planes being further from a center plane of the fin than the second one of the multiple parallel planes.

9. The structure of claim 7, wherein the second group is more distal from the major surface of the substrate than the first group, the first one of the multiple parallel planes being closer to a center plane of the fin than the second one of the multiple parallel planes.

10. The structure of claim 7, wherein a third group of the atoms is in the first one of the multiple parallel planes, the second group being disposed between the first group and the second group.

11. The structure of claim 7, wherein the first group comprises between 2 atoms and 20 atoms continuously in the second surface portion along an axis normal to the major surface of the substrate.

13. The structure of claim 7, wherein the second surface portion of the sidewall of the fin is a channel region, the channel region comprising the atoms in the multiple parallel planes.

14. A structure comprising:

a fin on a substrate, the fin having a first surface portion of a sidewall and a second surface portion of the sidewall, the first surface portion being in a plane, the second surface portion comprising at least one lattice shift away from the plane;

a gate dielectric on the second surface portion of the sidewall;

a gate electrode on the gate dielectric; and

an isolation region in the substrate, the isolation region adjoining the first surface portion of the sidewall proximate an upper surface of the isolation region.

15. The structure of claim 14, wherein the isolation region consists of a dielectric material.

16. The structure of claim 14, wherein the at least one lattice shift comprises a plurality of inward shifts relative to a center of the fin above the isolation region.

17. The structure of claim 14, wherein the at least one lattice shift comprises a plurality of outward shifts relative to a center of the fin above the isolation region.

18. The structure of claim 14, wherein the at least one lattice shift comprises a combination of inward shifts relative to a center of the fin and outward shifts relative to the center of the fin above the isolation region.

19. The structure of claim 14, wherein the at least one lattice shift comprises a lattice shift of more than one lattice spacings above the isolation region.