Merged active devices on a common substrate

• US 8,987,792 B2
• Filed: 03/14/2013
• Issued: 03/24/2015
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Adamski, Jaroslaw, Olson, Chris
• Primary Examiner(s): Nhu, David
• Application Number:
  US13/826,566
• Publication Number:
  US 20140264625A1
• Time in Patent Office: 740 Days
• Field of Search: 257/288, 257/277, 257/322, 257/341, 257/274, 257/192, 257/401, 257/E21.027, 257/E21.042, 257/E21.051, 257/E21.058, 257/E21.061, 257/E21.37, 257/E21.4, 257/E21.421, 257/E21.632
• US Class Current: 257/288
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate

Abstract

Merged active devices on a common substrate are presented. Methods for operating and fabricating such merged active devices are also presented.

Claims

1. An arrangement of gates, comprising:

a plurality of gates corresponding to stacked devices, wherein the stacked devices are stacked across an active area common to the plurality of gates;

a plurality of conducting channels formed, during operation of the arrangement, underneath each gate from among the plurality of gates;

a first source contact in correspondence of a first gate from among the plurality of gates;

a last drain contact in correspondence of a last gate from among the plurality of gates;

a first drain side of the active area in correspondence of the first gate;

a last source side of the active area in correspondence of the last gate; and

one or more drain sides and one or more source sides of the active area, wherein each drain side and each source side is in correspondence of each gate other than the first gate and the last gate and form contiguous regions,

wherein, during operation of the arrangement, current is adapted to travel through the contiguous regions as well as through the plurality of conducting channels formed underneath each of corresponding gates overlapping the active area, and

wherein at least one of the stacked devices is different from the other stacked devices.

3. The arrangement according to claim 1, wherein the contiguous regions are devoid of respective drain contacts and source contacts.

2. An arrangement of gates, comprising:

a plurality of gates corresponding to stacked devices, wherein the stacked devices are stacked across an active area common to the plurality of gates;

a first source contact in correspondence of a first gate from among the plurality of gates;

a last drain contact in correspondence of a last gate from among the plurality of gates;

a first drain side of the active area in correspondence of the first gate;

a last source side of the active in correspondence of the last gate; and

one or more drain sides and one or more source sides of the active area, wherein each drain side and each source side is in correspondence of each gate other than the first gate and the last gate and form contiguous regions,

wherein at least one of the stacked devices is different from the other stacked devices.

4. The arrangement according to claim 2, wherein the contiguous regions are devoid of respective drain contacts and source contacts.

6. The arrangement according to claim 2, wherein all stacked devices are of a same type, the same type being chosen from among the group consisting of:

n-channel (or NMOS) devices and p-channel (or PMOS) devices.

7. The arrangement according to claim 6 wherein all stacked devices are of a same type, the same type being chosen from among the group consisting of:

normal devices and native devices.

8. The arrangement according to claim 2, wherein the at least one of the stacked devices has a different threshold voltage from the other stacked devices.

9. The arrangement according to claim 2, wherein the first gate corresponds to a normal device and other gates correspond to native devices.

10. The arrangement according to claim 9, wherein the first gate corresponds to a normal NMOS device and other gates correspond to native NMOS devices.

11. The arrangement according to claim 2, wherein the at least one of the stacked devices has a different gate oxide thickness'"'"' from the other stacked devices.

12. The arrangement according to claim 2, wherein the at least one of the stacked devices has a different gate length from the other stacked devices.

13. The arrangement according to claim 2, wherein the at least one of the stacked devices has a different gate width to length ratio (W/L) from the other stacked devices.

14. The arrangement according to claim 13, wherein the at least one of the stacked devices having a different gate width to length ratio (W/L) from the other stacked devices has a gate with a zigzag or wavelike shape and the other stacked devices have gates with a rectangular shape.

15. The arrangement according to claim 2, wherein the arrangement is characterized by at least two hybrid factors, each hybrid factor being selected from among the group consisting of:

different threshold voltage between different devices, different gate oxide thickness between different devices, different gate length between different devices, and different gate width to length (W/L) ratio between different devices.

16. The arrangement according to claim 2, adapted for use in an application selected from among the group consisting of:

an RF (radio frequency) amplifier, an RF power amplifier, a cellular RF power amplifier, a switching RF power amplifier, a CMOS (complementary metal oxide semiconductor) RF power amplifier, a cellular CMOS RF power amplifier, and a switching class E power amplifier.

5. An arrangement, comprising:

a plurality of N gates corresponding to stacked devices, wherein the stacked devices are stacked across an active area common to the plurality of N gates, wherein N represents an integer, at least one of the stacked devices being different from the other stacked devices;

a first source contact in correspondence of a first gate G₁ from among the plurality of N gates; and

a last drain contact in correspondence of a last gate G_N from among the plurality of N gates,

wherein, during operation of the arrangement, current travels between each of the plurality of gates through regions that are located between gates G₁ and G₂, . . . , and between gates G_N-1 and G_N, of the active area common to the plurality of N gates.