Non-planar gate all-around device and method of fabrication thereof

• US 8,987,794 B2
• Filed: 12/23/2011
• Issued: 03/24/2015
• Est. Priority Date: 12/23/2011
• Status: Active Grant

• Current Assignee: Sony Group Corp.
• Original Assignee: Intel Corporation
• Inventors: Rachmady, Willy, Pillarisetty, Ravi, Le, Van H., Kavalieros, Jack T., Chau, Robert S., Kachian, Jessica S.
• Primary Examiner(s): Potter, Roy
• Assistant Examiner(s): PATTON, PAUL E
• Application Number:
  US13/997,118
• Publication Number:
  US 20140225065A1
• Time in Patent Office: 1,187 Days
• US Class Current: 257/288
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0669 Nanowires or nanotubes carbon nanotubes as material of solid-state device active part H10K85/211
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. Channel nanowires having a third lattice are formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. The channel nanowires include a bottom-most channel nanowire and a bottom gate isolation is formed on the top surface of the substrate under the bottom-most channel nanowire. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding each channel nanowire.

Claims

1. A semiconductor device comprising:

a substrate having a top surface with a first lattice constant;

embedded epi source and drain regions disposed on the top surface of the substrate, said embedded epi source and drain regions having a second lattice constant that is different from the first lattice constant;

a plurality of channel nanowires having a third lattice constant that is different from the first lattice constant, wherein the third lattice constant is the same as the second lattice constant, said plurality of channel nanowires coupled to the embedded epi source and drain regions, and said plurality of channel nanowires including a bottom-most channel nanowire;

a gate dielectric layer disposed on and all-around each channel nanowire; and

,

a gate electrode disposed on the gate dielectric layer and surrounding each channel nanowire.

2. The device in claim 1, wherein said plurality of channel nanowires and said embedded epi source and drain regions are uniaxially lattice stressed in a direction parallel to the length of the plurality of channel nanowires and are lattice relaxed in a direction perpendicular to the length of the plurality of channel nanowires.

3. The device in claim 2, wherein the embedded epi source and drain regions provide a force on said plurality of channel nanowire.

4. The device in claim 3, wherein said embedded epi source and drain regions are [111]-faceted.

5. The device in claim 1, further comprising a bottom gate isolation disposed on the top surface of the substrate and under the bottom most channel nanowire wherein said bottom gate isolation has a thickness that is sufficiently thick to isolate the top surface of said substrate from capacitive coupling by said gate electrode.

6. The device in claim 1, wherein the second lattice constant and the third lattice constant are larger than the first lattice constant.

7. The device of claim 1, wherein the top surface of the substrate is SiGe, the plurality of channel nanowires are undoped Ge, and the embedded epi source and drain regions are Ge.

8. The device of claim 5 wherein the bottom gate isolation is silicon oxide.

9. A method of forming a semiconductor device comprising:

providing a substrate having a top surface with a first lattice constant and having a fin formed on the top surface of the substrate, said fin comprises alternating layers of a semiconductor material having a second lattice constant and a sacrificial material having a third lattice constant, wherein the second lattice constant is different from the first lattice constant and the third lattice constant;

forming a sacrificial gate electrode over a channel region of the fin;

forming a pair of sidewall spacers on opposite sides of said sacrificial gate electrode, wherein a sacrificial portion of the fin extends out from each of said sidewall spacers;

removing the sacrificial portion of the fin to expose source and drain regions of the substrate;

forming a embedded epi source and drain regions on said source and drain regions of the substrate, wherein said embedded epi source and drain regions are coupled to the fin and have a fourth lattice constant that is different from the first lattice constant, wherein the fourth lattice constant is the same as the second lattice constant;

removing said sacrificial gate electrode to expose the channel region of the fin;

removing the sacrificial material between the layers of semiconductor material in the channel region of the fin to form a plurality of channel nanowires, said plurality of channel nanowires includes a bottom-most channel nanowire;

depositing a gate dielectric layer all-around each channel nanowire; and

,

depositing a gate electrode on the gate dielectric layer and surrounding each channel nanowire.

10. The method of claim 9, wherein said fin has a length and wherein said fin is uniaxially lattice stressed in a direction parallel to the length of the fin and is lattice relaxed in a direction perpendicular to the length of the fin.

11. The method of claim 9, wherein said embedded epi source and drain regions are uniaxially lattice stressed in a direction parallel to the length of the fin and are lattice relaxed in a direction perpendicular to the length of the fin.

12. The method of claim 9, wherein said embedded epi source and drain regions provide a force on the plurality of channel nanowires, wherein said plurality of channel nanowires is uniaxially lattice stressed in a direction parallel to the length of the fin and is lattice relaxed in a direction perpendicular to the length of the fin, and wherein said force maintains the uniaxial lattice stress in the plurality of channel nanowires.

13. The method of claim 9, wherein removing the sacrificial portion of the fin to expose the source and drain regions of the substrate includes recessing the top surface of the substrate to form source and drain trenches, and wherein said embedded epi source and drain regions are formed in the source and drain trenches.

14. The method of claim 9, wherein the embedded epi source and drain regions are formed by epitaxial growth and is [111]-faceted.

15. The method of claim 9, further comprising forming a bottom isolation on the top surface of the substrate under the bottom most channel nanowire wherein said bottom gate isolation is formed having a thickness that is sufficiently thick to isolate the top surface of said substrate from capacitive coupling by said gate electrode.

16. The method of claim 9, wherein the second lattice constant and the fourth lattice constant are larger than the first lattice constant and the third lattice constant.

17. The method of claim 9, wherein the semiconductor material is a single crystalline semiconductor material having a carrier mobility greater than single crystalline silicon.

18. The method of claim 9, wherein the semiconductor material is undoped Ge, the sacrificial material is SiGe, the plurality of channel nanowires are undoped Ge, and the embedded epi source and drain regions are Ge.

19. The method of claim 15, wherein the bottom gate isolation is silicon oxide.

20. A semiconductor device comprising:

a substrate having a top surface with a first lattice constant;

a plurality of channel nanowires having a second lattice constant that is different than the first lattice constant, said plurality of said channel nanowires including a bottom channel nanowire;

a source and a drain disposed on opposite sides of said plurality of channel nanowires;

a bottom gate isolation disposed on the top surface of said substrate and under the bottom most channel nanowire;

a gate dielectric layer disposed on and around each channel nanowires; and

a gate electrode disposed on the gate dielectric layer and surrounding each channel nanowire said gate electrode disposed between said bottom channel nanowire and said bottom gate isolation.

21. The semiconductor device of claim 20 wherein said plurality of channel nanowires are uniaxially stressed in a direction parallel to the length of the plurality of channel nanowires and are substantially lattice relaxed in a direction perpendicular to the length of the plurality of channel nanowires.

22. The semiconductor device of claim 20 wherein said source and drain are embedded epi source and drain regions.

23. The semiconductor device of claim 22 wherein the embedded epi source and drain regions are disposed in a trench.

24. The semiconductor device of claim 23 wherein the embedded epi source and drain regions are formed from a homogeneous semiconductor material having a third lattice constant which is greater than said first lattice constant.

25. The semiconductor device of claim 21 wherein said source and drain are formed of alternating layers of different semiconductor materials.

26. A method of forming a semiconductor device comprising:

providing a substrate having a top surface with a first lattice constant and having a fin formed on the top surface of the substrate, said fin comprising alternating layers of semiconductor material having a second lattice constant and a sacrificial material having a third lattice constant, wherein the second lattice constant is different from the first lattice constant and the third lattice constant;

forming a sacrificial gate electrode over a channel region of the fin;

forming a pair of sidewall spacers on opposite sides of said sacrificial gate electrode;

removing said sacrificial gate electrode to expose the channel region of the fin;

removing the sacrificial material between the layers of semiconductor material in the channel region of the fin to form a plurality of channel nanowires, said plurality of channel nanowires including a bottom most channel wire;

depositing a dielectric material over and around said plurality of channel nanowires;

etching said dielectric layer to remove said dielectric except on the top surface of the substrate under the bottom most channel nanowire to form a bottom gate isolation wherein said bottom gate isolation is not in physical contact with the bottom most channel nanowire;

depositing a gate dielectric layer all around each channel nanowire; and

depositing a gate electrode on the gate dielectric layer and surrounding each channel nanowire.

27. The method of claim 26 wherein said fin has a length and wherein said fin is uniaxially lattice stressed in a direction parallel to the length of the fin and is lattice relaxed in a direction perpendicular to the length of the fin.

28. The method of claim 26 further comprising forming a source region and a drain region in said fin on opposite sides of said sacrificial gate electrode.

29. The method of claim 26 wherein a sacrificial portion of the fin extends out from each of said sidewall spacers;

removing the sacrificial portion of the fin to expose source and drain regions of the substrate; and

forming embedded epi source and drain regions on said source and drain regions of the substrate, wherein the embedded epi source and drain regions are coupled to the fin and have fourth lattice constant that is different from said first lattice constant.