Copper pillar full metal via electrical circuit structure

• US 8,987,886 B2
• Filed: 03/07/2012
• Issued: 03/24/2015
• Est. Priority Date: 06/02/2009
• Status: Active Grant

• Current Assignee: HSIO Technologies LLC
• Original Assignee: HSIO Technologies LLC
• Inventors: Rathburn, James
• Primary Examiner(s): Lee, Jae
• Assistant Examiner(s): Mirsalahuddin, Junaiden
• Application Number:
  US13/413,724
• Publication Number:
  US 20120168948A1
• Time in Patent Office: 1,112 Days
• Field of Search: 257/625, 257/676, 257/666, 257/671, 257686-690, 257/672, 257/772, 257/734, 257/737, 257/738, 257/774, 257/778, 257779-785, 257/E27.137, 257/E27.144, 257/E27.161, 257/E23.015, 257/E23.02, 257E23023-E23079, 257/E23.021, 257/E21.508, 257E23169-E23178, 257E21575-E21597, 257/E21.627, 257/E21.641, 438/6, 438/128, 438/598, 438613-618, 438/629, 438/637.672
• US Class Current: 257/691
• CPC Class Codes: G02B 6/3608 Fibre wiring boards, i.e. where fibres are embedded or attached in a pattern on or to a substrate, e.g. flexible sheets optical ribbon cables in support members G02B6/4401
• CPC Class Codes: G02B 6/4281 the printed circuit boards being flexible in general H05K1/147
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 2223/6627 Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/08235 the bonding area connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/1132 Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48235 connecting the wire to a via metallisation of the item
• CPC Class Codes: H01L 2224/81192 wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

An electrical interconnect including a first circuitry layer with a first surface and a second surface. At least a first dielectric layer is printed on the first surface of the first circuitry layer to include a plurality of first recesses. A conductive material is deposited in a plurality of the first recesses to form a plurality of first conductive pillars electrically coupled to, and extending generally perpendicular to, the first circuitry layer. At least a second dielectric layer is printed on the first dielectric layer to include a plurality of second recesses generally aligned with a plurality of the first conductive pillars. A conductive material is deposited in a plurality of the second recesses to form a plurality of second conductive pillars electrically coupled to, and extending parallel the first conductive pillars.

Claims

1. A method of making an electrical interconnect comprising the steps of:

providing a first circuitry layer comprising a first surface and a second surface;

applying at least a first dielectric layer on the first surface of the first circuitry layer to include a plurality of first recesses;

plating a conductive material that substantially fills a plurality of the first recesses comprising a plurality of first conductive pillars electrically coupled to, and extending generally perpendicular to, the first circuitry layer;

planarizing the first conductive pillars and the first dielectric layer before applying the second dielectric layer;

applying at least a second dielectric layer on the first dielectric layer to include a plurality of second recesses generally aligned with a plurality of the first conductive pillars;

plating a conductive material that substantially fills a plurality of the second recesses comprising a plurality of second conductive pillars electrically coupled to, and extending parallel to the first conductive pillars; and

electrically coupling contact pads on an IC device to a plurality of the second conductive pillars.

2. The method of claim 1 comprising the step of printing at least one electrical device on one of the dielectric layers and electrically coupling the printed electrical device to at least a portion of the first circuitry layer.

3. The method of claim 1 comprising the steps of:

locating a second circuitry layer on the second dielectric layer and electrically coupling the second circuitry layer with a plurality of the second conductive pillars; and

applying at least a third dielectric layer on the second dielectric layer to include a plurality of third recesses generally aligned with a plurality of the second conductive pillars.

4. The method of claim 3 comprising etching away portions of the second circuitry layer located in the third recesses away to expose a plurality of the second conductive pillars.

5. The method of claim 3 comprising the steps of:

plating a conductive material in a plurality of the third recesses comprising a plurality of third conductive pillars electrically coupled to, and extending parallel the second conductive pillars; and

electrically coupling contact pads on an IC device to a plurality of the third conductive pillars, wherein the step of electrically coupled comprises one of a flip chip attachment directly to a plurality of third pillars, solder balls, or wire bonding.

6. The method of claim 3 comprising the steps of:

locating a third circuitry layer on the third dielectric layer; and

attaching a covering layer to the third circuitry layer, the covering layer comprising a plurality of openings exposing contact pads on the third circuitry layer configured to electrically couple with an IC device.

7. The method of claim 1 comprising attaching a covering layer to the second surface of the first circuitry layer, the covering layer comprising a plurality of openings exposing a plurality of contact pads on the first circuitry layer adapted to electrically couple with a PCB.

8. The method of claim 1 comprising locating a dielectric material in one or more of the recesses to surround one or more conductive pillars.

10. The method of claim 1 comprising the step of plating sidewalls of the first recesses to facilitate plating of the first conductive pillars.

11. The method of claim 1 comprising the step of planarizing the second conductive pillars and the second dielectric layer.

9. A method of making an electrical interconnect comprising the steps of:

providing a first circuitry layer comprising a first surface and a second surface;

applying a first liquid dielectric layer on the first surface of the first circuitry layer;

imaging the first liquid dielectric layer to form a first dielectric layer with a plurality of first recesses;

plating a conductive material that substantially fills a plurality of the first recesses comprising a plurality of first conductive pillars electrically coupled to, and extending generally perpendicular to, the first circuitry layer;

planarizing the first conductive pillars and the first dielectric layer;

applying a second liquid dielectric layer on the first dielectric layer;

imaging the second liquid dielectric layer to form second dielectric layer with a plurality of second recesses generally aligned with a plurality of the first conductive pillars; and

plating a conductive material that substantially fills a plurality of the second recesses comprising a plurality of second conductive pillars electrically coupled to, and extending from the first conductive pillars; and

printing at least one electrical device on one of the dielectric layers and electrically coupling the electrical device to at least a portion of the circuitry layers.

12. A method of making an electrical interconnect comprising the steps of:

providing a first circuitry layer comprising a first surface and a second surface;

applying a first liquid dielectric layer on the first surface of the first circuitry layer;

imaging the first liquid dielectric layer to form a plurality of first recesses;

plating sidewalls of the first recesses;

plating a conductive material that substantially fills a plurality of the first recesses comprising a plurality of first conductive pillars electrically coupled to, and extending generally perpendicular to, the first circuitry layer;

planarizing the first conductive pillars and the first dielectric layer;

applying a second liquid dielectric layer on the first dielectric layer;

imaging the second liquid dielectric layer to form a plurality of second recesses generally aligned with a plurality of the first conductive pillars; and

plating a conductive material that substantially fills a plurality of the second recesses comprising a plurality of second conductive pillars electrically coupled to, and extending from the first conductive pillars.