Semiconductor package

• US 8,987,897 B2
• Filed: 05/17/2011
• Issued: 03/24/2015
• Est. Priority Date: 11/24/2010
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Chan, Kuei-Ti, Lin, Tzu-Hung, Huang, Ching-Liou
• Primary Examiner(s): SMITH, BRADLEY
• Application Number:
  US13/109,740
• Publication Number:
  US 20120126368A1
• Time in Patent Office: 1,407 Days
• Field of Search: 257/737
• US Class Current: 257/737
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/0346 Plating
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05082 Two-layer arrangements
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11912 the bump being used as a mask for patterning other parts
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/3171 : the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/645 : Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 23/66 : High-frequency adaptations
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12 : Passive devices, e.g. 2 terminal devices
• CPC Class Codes: H01L 2924/1206 : Inductor
• CPC Class Codes: H01Q 23/00 : Antennas with active circuits or circuit elements integrated within them or attached to them

Abstract

The invention provides a semiconductor package. The semiconductor package includes a substrate. A first passivation layer is disposed on the substrate. An under bump metallurgy layer is disposed on the first passivation layer. A passive device is disposed on the under bump metallurgy layer.

Claims

1. A semiconductor package, comprising:

a substrate;

a first passivation layer disposed on the substrate;

an under bump metallurgy layer disposed on the first passivation layer;

a passive device disposed on the under bump metallurgy layer;

an additional under bump metallurgy layer disposed on the first passivation layer, isolated from the under bump metallurgy layer;

a conductive bump disposed on the additional under bump metallurgy layer; and

a conductive pillar disposed between the additional under bump metallurgy layer and the conductive bump, wherein the conductive pillar and the passive device are at the same level.

2. The semiconductor package as claimed in claim 1, further comprises an interconnection structure between the substrate and the first passivation layer, wherein the interconnection structure comprises a plurality of metal layers and a plurality of dielectric layers.

3. The semiconductor package as claimed in claim 2, wherein the interconnection structure comprises a metal pad formed by an uppermost metal layer of the metal layers of the interconnection structure.

4. The semiconductor package as claimed in claim 3, wherein the metal pad is exposed from a first opening of the first passivation layer.

5. The semiconductor package as claimed in claim 3, wherein the under bump metallurgy covers the metal pad exposed from the first opening, extending over the first passivation layer.

6. The semiconductor package as claimed in claim 5, further comprises a third passivation layer disposed between the first passivation layer and the under bump metallurgy layer, wherein the third passivation layer has a second opening to expose a portion of the metal pad exposed from the first opening.

7. The semiconductor package as claimed in claim 6, wherein the first and second passivation layers comprise oxide, nitride, oxynitride, and wherein the third passivation layer comprises polyimide.

8. The semiconductor package as claimed in claim 3, further comprises a second passivation layer between the substrate and the metal pad, wherein the second passivation layer is formed by an uppermost dielectric layer of the dielectric layers of the interconnection structure.

9. The semiconductor package as claimed in claim 3, wherein the passive device has two terminals respectively connected to the metal pad and an additional metal pad disposed on the top of the interconnection structure.

10. The semiconductor package as claimed in claim 3, wherein the passive device has two terminals respectively connected to the metal pad and a metal pad of a print circuit board disposed over the passive device.

11. The semiconductor package as claimed in claim 3, wherein the passive device has two terminals respectively connected to different metal pads of a print circuit board disposed over the passive device.

12. The semiconductor package as claimed in claim 1, wherein the passive device is formed of copper.

13. The semiconductor package as claimed in claim 2, wherein the passive device comprises a connecting segment crossing with a portion of the passive device.

14. The semiconductor package as claimed in claim 13, wherein the crossing segment is formed by an uppermost metal layer of the metal layers of the interconnection structure.

15. The semiconductor package as claimed in claim 1, further comprises a solder covering the passive device.

16. The semiconductor package as claimed in claim 15, wherein the conductive bump and the solder are at the same level.

17. The semiconductor package as claimed in claim 1, wherein the under bump metallurgy fully overlaps with the passive device.

18. The semiconductor package as claimed in claim 1, wherein the copper pillar comprises an inductor or an antenna.

19. A semiconductor package, comprising:

an under bump metallurgy layer disposed on a substrate;

a passive device disposed on the under bump metallurgy layer;

a solder disposed on the passive device;

an additional under bump metallurgy layer disposed on the substrate, isolated from the under bump metallurgy;

a conductive bump disposed on the additional under bump metallurgy; and

a conductive pillar disposed between the additional under bump metallurgy and the conductive bump, wherein the conductive pillar and the passive device are at the same level.

20. The semiconductor package as claimed in claim 19, wherein the passive device has two terminal respectively connecting to different metal pads disposed between the under bump metallurgy and the substrate.

21. The semiconductor package as claimed in claim 19, wherein the passive device has two terminal respectively connecting to a metal pad disposed between the under bump metallurgy and the substrate and a metal pad of a print circuit board disposed over the passive device.

22. The semiconductor package as claimed in claim 19, wherein the passive device has two terminals respectively connected to different metal pads of a print circuit board disposed over the passive device.

23. The semiconductor package as claimed in claim 19, wherein the passive device is formed of copper.

24. The semiconductor package as claimed in claim 19, wherein the copper pillar comprises an inductor or an antenna.