Bumped semiconductor wafer or die level electrical interconnect

• US 8,988,093 B2
• Filed: 03/06/2012
• Issued: 03/24/2015
• Est. Priority Date: 06/02/2009
• Status: Active Grant

• Current Assignee: HSIO Technologies LLC
• Original Assignee: HSIO Technologies LLC
• Inventors: Rathburn, James
• Primary Examiner(s): Nguyen, Tung X
• Application Number:
  US13/413,032
• Publication Number:
  US 20120182035A1
• Time in Patent Office: 1,113 Days
• Field of Search: 32476201-7621, 32475401-7543, 32475501-75511
• US Class Current: 324/755.01
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence

Abstract

A probe assembly that acts as a temporary interconnect between terminals on an IC device and a test station. The probe assembly includes a plurality of stud bumps arranged on a first surface of a substrate in a configuration corresponding to the terminal on the IC device. The stud bumps include a shape adapted to temporarily couple with the terminals on the IC device. A plurality of conductive traces on the substrate electrically couple the stud bumps with the test station.

Claims

1. A probe assembly to act as a temporary interconnect between terminals on an IC device and a test station, the probe assembly comprising:

a substrate comprising a dielectric material;

a plurality of conductive stud bumps arranged on a first surface of the substrate in a configuration corresponding to the terminal on the IC device, the stud bumps comprising a shape adapted to temporarily couple with the terminals on the IC device;

a plurality of conductive traces located on the substrate electrically coupled with the test station and proximal ends of one or more of the stud bumps; and

a compliant layer supporting the proximal ends of the stud bumps, the compliant layer adapted to elastically bias the stud bumps toward the terminals on the circuit member and to compensate for non-planarity of the terminal.

2. The probe assembly of claim 1 comprising a protective layer deposited on the compliant layer.

3. The probe assembly of claim 1 wherein the substrate comprises a multi-layered structure.

4. The probe assembly of claim 3 wherein the substrate comprises a conductive material and a non-conductive material located on a single layer of the probe assembly.

5. The probe assembly of claim 3 wherein the multi-layered structure comprises at least one additional circuitry plane comprising one of a ground plane, a power plane, an electrical connection to other circuit members, a dielectric layer, and a flexible circuit.

6. The probe assembly of claim 1 further comprising a flexible circuit member electrically coupled to the conductive traces and extending beyond a perimeter edge of the probe assembly.

7. The probe assembly of claim 1 further comprising a plurality of electrical devices located on the probe assembly and electrically coupled to one or more of the conductive traces.

8. The probe assembly of claim 7 wherein the electrical devices are selected from the group consisting of a power plane, ground plane, capacitor, resistor, filters, signal or power altering and enhancing device, capacitive coupling feature, memory device, embedded integrated circuit, and RF antennae.

9. The probe assembly of claim 1 further comprising a plurality of electrical devices printed on one or more of the layers and electrically coupled to at least one of the stud bumps.

10. A test system comprising:

a housing comprising an opening adapted to retain the IC device;

an IC device located in the openings in the housing and electrically coupled to the stud bumps on the probe assembly of claim 1; and

a test station electrically coupled to the conductive traces that is adapted to evaluate the IC device.

11. A testing system comprising:

a probe assembly comprising;

a substrate comprising a dielectric material;

a plurality of conductive stud bumps arranged on a first surface of the substrate in a configuration corresponding to the terminal on the IC device, the stud bumps comprising a shape adapted to temporarily couple with the terminals on the IC device;

a plurality of conductive traces located on the substrate electrically coupled with proximal ends of one or more of the stud bumps; and

a compliant layer supporting the proximal ends of the stud bumps, the compliant layer adapted to bias the stud bumps toward the terminals on the circuit member and to compensate for non-planarity of the terminal;

an IC device comprising terminals compressively engaged with distal ends of the stud bumps, the compliant layer biasing the stud bumps toward terminals on the IC device and to compensate for non-planarity of the terminals; and

a test station electrically coupled to the conductive traces of the probe assembly configured to test the IC device.

12. The test system of claim 11 comprising a protective layer deposited on the compliant layer.

13. The test system of claim 11 wherein the substrate comprises a multi-layered structure.

14. The test system of claim 13 wherein the substrate comprises a conductive material and a non-conductive material located on a single layer of the probe assembly.

15. The test system of claim 13 wherein the multi-layered structure comprises at least one additional circuitry plane comprising one of a ground plane, a power plane, an electrical connection to other circuit members, a dielectric layer, and a flexible circuit.

16. The test system of claim 11 further comprising a flexible circuit member electrically coupled to the conductive traces and extending beyond a perimeter edge of the probe assembly.

17. The test system of claim 11 further comprising a plurality of electrical devices located on the probe assembly and electrically coupled to one or more of the conductive traces.

18. The test system of claim 17 wherein the electrical devices are selected from the group consisting of a power plane, ground plane, capacitor, resistor, filters, signal or power altering and enhancing device, capacitive coupling feature, memory device, embedded integrated circuit, and RF antennae.

19. The test system of claim 11 further comprising a plurality of electrical devices printed on one or more of the layers and electrically coupled to at least one of the stud bumps.