Capacitively coupled logic gate

• US 8,988,103 B2
• Filed: 09/15/2011
• Issued: 03/24/2015
• Est. Priority Date: 09/15/2010
• Status: Active Grant

• Current Assignee: Jonker LLC
• Original Assignee: David Liu
• Inventors: Liu, David K. Y.
• Primary Examiner(s): Taningco, Alexander H
• Assistant Examiner(s): LO, CHRISTOPHER KWOK YEUNG
• Application Number:
  US13/233,767
• Publication Number:
  US 20120062276A1
• Time in Patent Office: 1,286 Days
• Field of Search: 326/93, 326 95- 98, 326104-108, 326/121, 326 9- 11, 326 35- 36
• US Class Current: 326/36
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H03K 19/173 using elementary logic circuits as components
• CPC Class Codes: H03K 19/23 Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates

Abstract

An electronic logic circuit uses areal capacitive coupling devices coupled together to process a set of data inputs. Each areal capacitive coupling device can be configured such that a floating gate potential of such device can be altered to at least a first state or a second state in response to receiving an input signal from the set of data inputs, which is coupled electrically to the floating gate. A majority function logic circuit (and other similar circuits) can be interconnected this way using far fewer gates than with a conventional CMOS implementation. Selective logic gates can also be enabled or disabled by configuring them effectively as memory devices.

Claims

1. An electronic logic circuit comprising:

a. a plurality of interconnected two terminal areal capacitive coupling devices coupled to a set of data inputs;

each of said two terminal areal capacitive coupling devices comprising;

i) a floating gate; and

ii) an n-type impurity source coupled to a first terminal; and

iii) an n-type impurity drain coupled to a second terminal and

wherein the n-type impurity drain overlaps a sufficient portion of said floating gate and is configured to impart an input signal voltage applied to said second terminal of said n-type impurity drain and said first terminal to said floating gate through areal capacitive coupling and cause each of said areal capacitive coupling devices to be placed into a first state;

further wherein an output of each two terminal areal capacitive coupling device is related to said first state or said second state, and said plurality of interconnected two terminal areal capacitive devices are configured to generate a plurality of separate outputs;

said plurality of separate outputs of said plurality of interconnected two terminal areal capacitive coupling devices being adapted to effectuate a collective output corresponding to an output which is a first logical function associated with the set of data inputs applied to said plurality of interconnected two terminal areal capacitive coupling devices.

2. The electronic logic circuit of claim 1, wherein said plurality of interconnected two terminal areal capacitive coupling devices are embedded with other CMOS devices having gates made of a material that is shared with said floating gate.

3. The electronic logic circuit of claim 1, wherein at most N interconnected two terminal areal capacitive coupling devices are included to process N separate and unique inputs.

4. The electronic logic circuit of claim 1, wherein said first logical function is a majority function effectuated on said set of data inputs.

5. The electronic logic circuit of claim 1, wherein said logic function is associated with a value from a lookup table.

6. The electronic logic circuit of claim 1, further including a FET and an inverter stage coupled to said collective output, said FET being configured to drive said inverter stage to a first logical output in response to a first value of said collective output.

7. The electronic logic circuit of claim 1, wherein said plurality of interconnected two terminal areal capacitive coupling devices include a gated diode which has direct coupling of said floating gate to a first active region potential receiving said input signal.

13. The electronic logic circuit of claim 6 wherein said FET has a pulldown characteristic matched to said collective output.

14. The electronic logic circuit of claim 1 wherein an output current of the plurality of interconnected two terminal areal capacitive coupling devices is configured by a coupling capacitance between said floating gate and said n-type impurity drain.

15. The electronic logic circuit of claim 1 wherein the plurality of interconnected two terminal areal capacitive coupling devices are manufactured as part of a CMOS logic process.

16. The electronic logic circuit of claim 1 wherein one of the set of data inputs acts as a function select signal to dynamically adjust behavior of a corresponding two terminal areal capacitive coupling device.

17. The electronic logic circuit of claim 4 wherein a device count used to implement an N input majority function gate is equal to N capacitive coupling devices and an additional set of 5 support transistors.

18. The electronic logic circuit of claim 1 wherein a device count used to implement an N input majority function gate in the electronic logic circuit is equal to N capacitive coupling devices and an additional set of 5 support transistors.

8. A majority function logic circuit comprising:

a. a plurality of two terminal areal capacitive coupling devices interconnected in parallel to a set of separate data inputs;

each of said two terminal areal capacitive coupling devices comprising;

i) a floating gate; and

ii) an n-type impurity source coupled to a first terminal; and

iii) an n-type impurity drain coupled to a second terminal and

wherein the n-type impurity drain overlaps a sufficient portion of said floating gate and is configured to impart an input signal voltage applied to said second terminal of said n-type impurity drain and said first terminal to said floating gate through areal capacitive coupling and cause each of said areal capacitive coupling devices to be placed into a first state;

said plurality of interconnected two terminal areal capacitive coupling devices being adapted to generate an output which is a majority function associated with the set of separate data inputs;

wherein said output has a first logical value when a majority of said set of separate data inputs exceed a predetermined voltage potential, and said output has a second logical value when a majority of said set of separate data inputs does not exceed said predetermined voltage potential.

19. The majority electronic logic circuit of claim 8 wherein a device count used to implement an N input majority function gate is equal to N capacitive coupling devices and an additional set of 5 support transistors.

9. A majority function silicon based semiconductor electronic logic circuit comprising:

a plurality of two terminal areal capacitive coupling devices coupled to process a set of separate data inputs, each of said separate data inputs having at least two distinct logic values, including a first logic value and a second logic value;

each two terminal areal capacitive coupling device being configured to alter a floating gate logic value of such device can be altered in response to receiving an input signal from said set of data inputs;

wherein said floating gate is configured to place a logic value of said two terminal areal capacitive coupling device into a first state or a second state through areal capacitive coupling to a potential associated with a first active region receiving said input signal;

wherein said plurality of two terminal areal capacitive coupling devices are interconnected to generate a collective output which has a first value when a majority of said set of separate data inputs have said first logical value, and said collective output has a second value when a majority of said set of separate data inputs has said second logical value;

the circuit being further configured to reduce a number of valid inputs in the set of data inputs by selectively electrically disabling any two terminal areal capacitive devices representing said invalid inputs.

10. The circuit of claim 9 where the two terminal areal capacitive device representing a given input is subjected to hot electron injection unto the floating gate to cause the input to be disabled by its two terminal areal capacitive device becoming non-conducting.

11. The method circuit of claim 9 where a first subset of the set of data inputs to the majority function electronic logic circuit is processed for a first operation, and a second subset of the set of data inputs is processed for a second operation by the majority function electronic logic circuit.

12. The circuit of claim 9 where the majority function electronic logic circuit can process any selected and enabled subset of available data inputs.

20. The electronic logic circuit of claim 9 wherein a device count used to implement an N input majority function gate is equal to N capacitive coupling devices and an additional set of 5 support transistors.