Ring oscillator with NMOS or PMOS variation insensitivity

• US 8,988,153 B1
• Filed: 03/09/2013
• Issued: 03/24/2015
• Est. Priority Date: 03/09/2013
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: SuVolta, Inc.
• Inventors: Roy, Richard S.
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US13/792,006
• Time in Patent Office: 745 Days
• Field of Search: 327/537, 331/57, 331/185, 331/2, 331/46, 365/189.011, 365/154
• US Class Current: 331/57
• CPC Class Codes: H03K 3/0315 Ring oscillators

Abstract

A low voltage ring oscillator circuit can have a frequency variation that depends on process variations of insulated gate field effect transistors (IGFETs) of a first conductivity type without substantially being affected by process variations to IGFETs of a second conductivity type. A ring oscillator stage may include an inverter including only IGFETs of the first conductivity type. The inverter may be coupled to a boot circuit that boosts the gate potential of a first IGFET of the first conductivity type with a timing such that IGFETs of the second conductivity type in the boot circuit do not affect the frequency variations of the ring oscillator circuit.

Claims

1. A method of setting a body bias potential, comprising the step of:

determining the frequency of a first ring oscillator by probing an output pad coupled to the ring oscillator;

setting a first predetermined body bias potential for a first conductivity type insulated gate field effect transistor (IGFET) in response to the frequency of the first ring oscillator by programming a first programmable voltage generator that provides the first predetermined body biased potential based on a first programming state; and

providing a supply voltage to the ring oscillator of less than 1.0 volt.

2. The method of claim 1, wherein

the IGFET includes a structure having a gate overlying a channel, wherein the channel comprises a substantially undoped channel having a relatively high mobility and a heavily doped screen layer lying a predetermined distance below the transistor gate;

and

the channel includes a heavily doped region at a dopant concentration sufficient to define a depletion depth when a voltage is applied to the gate.

3. The method of claim 1, further including the step of:

dicing a wafer wherein the first ring oscillator is located in a scribe line of the wafer and the first ring oscillator is destroyed in the step of dicing.

4. The method of claim 1, further including the step of:

setting a second predetermined body bias potential for a second conductivity type insulated gate field effect transistor (IGFET) in response to a frequency of a second ring oscillator.

5. The method of claim 4, wherein:

the step of setting a second predetermined body bias potential can include programming a second programmable voltage generator that provides the second predetermined body bias potential based on a second programming state.

6. A method of claim 4, further including the step of:

determining the frequency of the first ring oscillator; and

determining the frequency of the second ring oscillator wherein

the frequency of the first ring oscillator is substantially determined by characteristics of at least one IGFET of the first conductivity type and the frequency of the second ring oscillator is substantially determined by characteristics of at least one IGFET of the second conductivity type.

7. The method of claim 4, wherein:

the first conductivity type IGFET further including a first heavily doped region and structure below a first substantially undoped channel; and

the second conductivity type IGFET further including a second heavily doped region and structure below a second substantially undoped channel.

8. A ring oscillator circuit including a plurality of ring oscillator stages, at least one ring oscillator stage comprising:

an inverter circuit coupled to receive an output from a first previous output terminal of a first previous ring oscillator stage at an input terminal and provide an output at an output terminal coupled to a subsequent input terminal of a subsequent ring oscillator stage, the inverter circuit including

a first insulated gate field effect transistor (IGFET) having a first conductivity type, the first IGFET having a source terminal coupled to a first potential, a drain terminal coupled to the output terminal, and a gate terminal coupled to the input terminal; and

a second IGFET of the first conductivity type having a source terminal coupled to the output terminal, a drain terminal coupled to a second potential, and a gate terminal coupled to a boot node, the boot node receives a boosted potential outside the bounds of the first potential and the second potential.

9. The ring oscillator circuit of claim 8, wherein:

the at least one ring oscillator stage further includes

a boot circuit coupled to receive a first boot control signal and provide the boosted potential.

10. The ring oscillator circuit of claim 9, wherein:

the first boot control signal is provided by a second previous output terminal of a second previous ring oscillator stage.

11. The ring oscillator circuit of claim 9, wherein:

the boot circuit includes a boot capacitor having a first terminal coupled to the boot node.

12. The ring oscillator circuit of claim 11, wherein:

the boot capacitor is formed from a third IGFET having the first conductivity type.

13. The ring oscillator circuit of claim 11, wherein:

the boot circuit further includes

a first logic gate coupled to receive the first boot control signal and a second boot control signal and provides a first logic gate output; and

a charge circuit coupled to receive the first logic gate output at an input and having an output coupled to the first terminal of the boot node, the charge circuit provides charge to the first terminal of the boot capacitor.

14. The ring oscillator circuit of claim 13, wherein:

the first boot control signal is provided by a second previous output terminal of a second previous ring oscillator stage; and

the second boot control signal is provided by a third previous output terminal of a third previous ring oscillator stage.

15. The ring oscillator circuit of claim 14, wherein:

the first logic gate provides a first logic gate output having a predetermined pulse width at a first logic level and the charging circuit charges the first terminal of the boot capacitor in response to the first logic gate output having the first logic level.

16. The ring oscillator circuit of claim 13, wherein:

the boot control circuit further includes a boot drive circuit having an input coupled to receive the first logic gate output and providing a kick output to a second terminal of the boot capacitor.

17. The ring oscillator circuit of claim 9, wherein:

the boot circuit includes at least one IGFET having a second conductivity type and the inverter circuit has a propagation delay substantially determined by characteristics of IGFETs of the first conductivity type without substantially being affected by characteristics of IGFETs of the second conductivity type and a potential difference between the first potential and the second potential is less than 1.0 volt.