Successive approximation register (SAR) analog-to-digital converter (ADC) having optimized filter
First Claim
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1. A system comprising:
- a variable impedance controllable by a manual tuning mechanism to provide an analog signal; and
an analog-to-digital converter (ADC) coupled to the variable impedance to receive the analog signal, the ADC including;
a comparator to compare the analog signal received at a first input with a feedback signal received at a second input;
a successive approximation register (SAR) coupled to the comparator and having N-bits of resolution, wherein the SAR is to update a bit of an N-bit output based on the comparison;
a delta-sigma modulator (DSM) coupled to the SAR to receive the N-bit output of the SAR and to generate an output; and
a digital-to-analog converter (DAC) coupled to the DSM to convert the output to the feedback signal; and
a low pass filter (LPF) to filter and output the feedback signal to the second input of the comparator.
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Abstract
A system such as a mechanically tuned radio can have a signal path to receive and process an incoming radio frequency (RF) signal and to provide the processed signal to a first analog-to-digital converter (ADC) to convert the processed signal to a digital signal and to digitally demodulate the digital signal to obtain an audio signal, where this first ADC is separate from an auxiliary ADC not part of the signal path.
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Citations
20 Claims
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1. A system comprising:
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a variable impedance controllable by a manual tuning mechanism to provide an analog signal; and an analog-to-digital converter (ADC) coupled to the variable impedance to receive the analog signal, the ADC including; a comparator to compare the analog signal received at a first input with a feedback signal received at a second input; a successive approximation register (SAR) coupled to the comparator and having N-bits of resolution, wherein the SAR is to update a bit of an N-bit output based on the comparison; a delta-sigma modulator (DSM) coupled to the SAR to receive the N-bit output of the SAR and to generate an output; and a digital-to-analog converter (DAC) coupled to the DSM to convert the output to the feedback signal; and a low pass filter (LPF) to filter and output the feedback signal to the second input of the comparator. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method comprising:
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comparing an analog voltage signal received at a first input with a feedback signal received at a second input; updating a bit of a N-bit successive approximation register (SAR) based on the comparison; receiving an N-bit output of the SAR and generating a decision in a delta-sigma modulator (DSM); converting the decision to an analog signal; and filtering the analog signal to provide the feedback signal for the comparison. - View Dependent Claims (14, 15, 16)
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17. A system comprising:
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a signal path to receive and process an incoming radio frequency (RF) signal and to provide the processed signal to a first analog-to-digital converter (ADC) to convert the processed signal to a digital signal and to digitally demodulate the digital signal to obtain an audio signal; an auxiliary ADC to receive an analog signal from a potentiometer coupled to a battery voltage and user controllable to select a tuning frequency for a desired radio channel and to convert the analog signal to a digitized code, the auxiliary ADC including; a comparator having a first input to receive the analog signal and a second input to receive a feedback signal and to output a comparison signal; a successive approximation register (SAR) coupled to the comparator and having N-bits of resolution, wherein the SAR is to update a bit of the SAR based on the comparison signal; a delta-sigma modulator (DSM) coupled to the SAR to receive an N-bit output of the SAR and to generate an output; a digital-to-analog converter (DAC) coupled to the DSM to convert the DSM output to an analog feedback signal; and a low pass filter (LPF) coupled to the DAC to filter the analog feedback signal and to output the analog feedback signal to the second input of the comparator; and a microcontroller unit (MCU) coupled to the auxiliary ADC to receive the digitized code and to control at least one component of the signal path based thereon. - View Dependent Claims (18, 19, 20)
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Specification