Biasing scheme for large format CMOS active pixel sensors

• US 8,988,568 B2
• Filed: 07/03/2008
• Issued: 03/24/2015
• Est. Priority Date: 04/09/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Nakamura, Junichi, Takayanagi, Isao
• Primary Examiner(s): Ho, Tuan
• Assistant Examiner(s): GEBRIEL, SELAM T
• Application Number:
  US12/216,430
• Publication Number:
  US 20090002536A1
• Time in Patent Office: 2,455 Days
• Field of Search: 348294-324, 257/291, 257/292
• US Class Current: 348/294
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/671 for non-uniformity detection or correction
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
• CPC Class Codes: H04N 3/1568 for disturbance correction or prevention within the image-sensor, e.g. biasing, blooming, smearing correction circuits H04N25/62

Abstract

An image sensor includes circuitry compensating for voltage drops in a V_SS line. The image sensor includes a plurality of photoreceptors arranged in a pixel array having a number of column lines, and read-out circuitry on the column lines. The read-out circuitry provides substantially equal currents on each column line so as to compensate for voltage drops in the V_SS line and provide more accurate pixel signals. The image sensor also includes circuitry for filtering noise from a voltage supply line, and for providing hard and/or soft reset operations.

Claims

1. An image sensor comprising:

a pixel array including a plurality of column lines;

a plurality of load transistors, each coupling a respective one of the column lines to a ground line; and

a plurality of circuits, each respectively coupled to a gate of a load transistor, the plurality of circuits applying a substantially equal gate-source voltage to the gates of each of the load transistors.

2. A sensor as in claim 1, wherein the plurality of circuits each comprise a level shift circuit arranged between the ground line and a respective gate of a load transistor.

3. A sensor as in claim 1, wherein the plurality of circuits each comprise a clamp circuit arranged between the ground line and a respective gate of a load transistor.

16. A sensor as in claim 1, wherein the bulk of each load transistor is connected to its source.

17. A sensor as in claim 2, wherein, for a given column, a respective level shift circuit adds a pre-determined voltage to an input voltage from the ground line.

20. A sensor as in claim 1, wherein a voltage supplied by the plurality of circuits maintains a constant bias current through the load transistors.

4. An image sensor comprising:

a plurality of photoreceptors arranged in an array to form a plurality of columns of image sensors, each column of image sensors having readout circuitry that compensates for voltage drops in a ground line connecting the plurality of columns of image sensors, the readout circuitry comprising a plurality of load transistors each coupling a respective column of image sensors to the ground line, and a plurality of constant gate-source voltage supplying circuits respectively coupled between the ground line and the gates of the load transistors.

5. A sensor as in claim 4, wherein the plurality of constant gate-source voltage supplying circuits each comprise a level shift circuit connected between the ground line and the gate of a respective load transistor.

6. A sensor as in claim 4, wherein the plurality of constant gate-source voltage supplying circuits each comprise a clamp circuit.

7. A sensor as in claim 6, wherein each clamp circuit includes a clamp capacitor charged to a clamping voltage during a period when row select pulses are turned off.

8. A sensor as in claim 4, wherein each column of image sensors has reset circuitry that compensates for voltage drops in a voltage supply line.

9. A sensor as in claim 8, wherein the reset circuitry includes a hard reset switch provided in a voltage line to the pixel for hard resetting.

10. A sensor as in claim 9, wherein the hard reset switch comprises an n-MOS transistor operating in a saturation region.

11. A sensor as in claim 9, further comprising a soft reset switch provided in parallel to the hard reset switch.

12. A sensor as in claim 11, wherein the soft reset switch comprises a p-MOS transistor.

18. A sensor as in claim 4, wherein the bulk of each load transistor is connected to its source.

21. A sensor as in claim 4, wherein a voltage supplied by the constant gate-source voltage supplying circuits fluctuates to maintain a constant bias current through the load transistors.

13. A method of operating an image sensor comprising:

supplying a constant gate-source voltage to each of the gates of a plurality of load transistors each coupling a respective column of an image sensor array to a ground line such that a bias current flowing through each of the load transistors is substantially the same;

selecting a row to obtain a charge signal from a selected row of photoreceptors in the image sensor array; and

sampling a signal on each column of the selected row.

14. The method of claim 13, wherein the act of supplying is performed by a respective level shift circuit coupled between the ground line and a gate a respective load transistor.

19. The method of claim 13, wherein the gate-source voltage and a gate-bulk voltage of the load transistor are kept constant even if a voltage on the ground line rises.

15. A method of operating an image sensor comprising:

supplying a constant gate-source voltage to each of the gates of a plurality of load transistors each coupling a respective column of an image sensor array to a ground line such that a bias current flowing through each of the load transistors is substantially the same;

selecting a row to obtain a charge signal from a selected row of photoreceptors in the image sensor array; and

sampling a signal on each column of the selected row,

wherein the act of supplying is performed by a respective level shift circuit coupled between the ground line and a gate a respective load transistor, and

wherein an input of the level shift circuit for a given column i is V<sub>ss—

col—

i</sub> and an output is V<sub>ss—

col—

i</sub>+Δ

V, wherein Δ

V is a pre-determined voltage associated with the column.

22. The method of claim 15, wherein Δ

V for a first column line of the image sensor is different than Δ

V for at least one other column line of the image sensor.

23. An image sensor comprising:

a pixel array including a plurality of column lines;

a plurality of load transistors, each coupling a respective one of the column lines to a ground line; and

having a respective bias current passing therethrough; and

the plurality of circuits applying respective gate-source voltages to the gates of the load transistors such that a bias current passing through each of the load transistors is substantially the same.