Logic device having a compressed configuration image stored on an internal read only memory

• US 8,990,474 B2
• Filed: 12/02/2011
• Issued: 03/24/2015
• Est. Priority Date: 12/02/2011
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Ball, James L.
• Primary Examiner(s): Rossiter, Sean D
• Application Number:
  US13/310,574
• Publication Number:
  US 20130145074A1
• Time in Patent Office: 1,208 Days
• Field of Search: None
• US Class Current: 711/102
• CPC Class Codes: H03K 19/1776 for memories

Abstract

Systems and methods for using an internal read only memory (ROM) to configure a logic device are described. The ROM and the logic device may be located on a single chip. The ROM may be adapted to store highly compressed configuration images and be non-reprogrammable. The logic device may be configured based on the compressed configuration image.

Claims

1. A chip comprising:

a logic device;

a control block;

one or more mode select pins; and

a read only memory (ROM) storing a plurality of configuration images for the logic device, wherein

the ROM is non-reprogrammable;

at least one mode select pin of the one or more mode select pins is arranged to receive a selected mode, the selected mode being one or both of a boot mode and a configuration mode, and to cause the control block to select at least one configuration image from the plurality of configuration images stored in said ROM;

the at least one configuration image is used to configure the logic device; and

in the configuration mode, the control block is caused to avoid using uncompressed configuration information from a flash memory and is caused to use configuration information based on a compressed configuration image stored in the ROM.

2. The chip of claim 1, wherein the ROM comprises a mask ROM.

3. The chip of claim 1, wherein the logic device comprises at least one of a programmable logic device and a field programmable gate array.

4. The chip of claim 1, wherein said at least one configuration image is in compressed form.

5. The chip of claim 1, wherein the at least one configuration image is compressed.

6. The chip of claim 5, wherein the configuration image is compressed by a factor of at least 50.

7. The chip of claim 6, wherein the decompressor comprises a hardwired state machine.

8. The chip of claim 1 further comprising:

a decompressor adapted to decompress one or more compressed configuration images stored within said ROM to generate decompressed configuration information;

wherein

the decompressed configuration information is used to configure the logic device with the decompressed configuration information.

9. The chip of claim 8, wherein said at least one configuration image is in compressed form, and wherein the decompressor is adapted to decompress said at least one configuration image using a decompression software.

10. The chip of claim 9, wherein the decompression software is selected from the list consisting of gzip and bzip2.

11. The chip of claim 1, wherein the logic device comprises at least one interface controller, and the at least one configuration image is used to configure the at least one interface controller.

12. The chip of claim 11, wherein the interface controller comprises at least one of a memory interface controller and a communications interface controller.

13. The chip of claim 11, further comprising a processor adapted to use the interface controller to copy user-provided configuration information and boot code from a first external memory to a second external memory, wherein the first and second external memories are located outside the chip.

14. The chip of claim 13, wherein the second external memory comprises a dynamic random access memory (DRAM).

15. The chip of claim 13, wherein the processor is adapted to access the boot code from the second external memory to execute the boot software.

16. The chip of claim 13, wherein the processor is adapted to reconfigure the logic device with the user-provided configuration information.

17. A method comprising:

storing, within a non-reprogrammable read only memory (ROM), a plurality of compressed configuration images for a logic device, wherein the non-reprogrammable ROM and the logic device are each located within a single chip, the chip including a control block and one or more mode select pins;

acquiring configuration information from a selected one of the plurality of compressed configuration images, wherein at least one mode select pin of the one or more mode select pins is arranged receive a selected mode, the selected mode being one or both of a boot mode and a configuration mode, and to cause the control block to select at least one configuration image from the plurality of configuration images stored in said ROM;

configuring the logic device with the acquired configuration information; and

in the configuration mode, the control block is caused to avoid using uncompressed configuration information from a flash memory and is caused to use configuration information based on a compressed configuration image stored in the ROM.

18. The method of claim 17, wherein the logic device comprises at least one of a programmable logic device and a field programmable gate array.