Aliasing buffers

• US 8,990,515 B2
• Filed: 06/14/2011
• Issued: 03/24/2015
• Est. Priority Date: 06/14/2011
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: Agarwal, Amit Kumar, Zhu, Weirong, Levanoni, Yosseff
• Primary Examiner(s): Nahar, Qamrun
• Application Number:
  US13/160,373
• Publication Number:
  US 20120324430A1
• Time in Patent Office: 1,379 Days
• Field of Search: None
• US Class Current: 711/149
• CPC Class Codes: G06F 8/51 Source to source
• CPC Class Codes: G06F 9/44536 Selecting among different versions

Abstract

The present invention extends to methods, systems, and computer program products for aliasing buffers. Embodiment of the inventions supporting buffer aliasing through introduction of a level of indirection between a source program'"'"'s buffer accesses and the target executable physical buffers, and binding the logical buffer accesses to actual physical buffer accesses at runtime. A variety of techniques for can be used supporting runtime aliasing of buffers, in a system which otherwise disallows such runtime aliasing between separately defined buffers in the target executable code. Binding of logical buffer accesses in the source program to the actual physical buffers defined in the target executable code is delayed until runtime.

Claims

1. At a computer system including a plurality of processors and system memory, the plurality of processors including a first processor type and a second different processor type, the runtime environment for the second different processor type disallowing aliasing of physical data buffers, a method for aliasing a buffer, the method comprising:

accessing a program, the program including source code configured for mixed execution on the first processor type and the second different processor type, the source code defining a physical buffer, the source code also including aliasing instructions for logically accessing the physical buffer through a plurality of logical views, each logical view corresponding to a subset of data in the physical buffer, at least one portion of the source code containing the aliasing instructions targeted for execution in the runtime environment for the second different processor type disallowing aliasing of physical data buffers;

converting the at least one portion of source code into second code for the second different processor type, the second code defining a level of indirection between the logical buffer access and the physical buffer;

configuring execution of the second code within the runtime environment of the second different processor type to bind logical buffer access to the physical buffer using the defined level of indirection; and

using the defined level of indirection to bind the logical buffer access to the physical buffer during execution of the second code.

2. The method as recited in claim 1, wherein accessing a program comprises accessing a C++ program, the C++ being extended for parallel environments.

3. The method as recited in claim 1, wherein accessing a program comprises accessing a program configured for mixed execution in a Central Processing Unit (“

CPU”

) runtime and a Graphical Processing Unit (“

GPU”

) runtime.

4. The method as recited in claim 1, wherein accessing a program comprises accessing a program that includes instructions for logically accessing one of:

Random Access Memory (“

RAM”

) and virtual memory on a disk.

5. The method as recited in claim 1, wherein converting the at least one portion of source code into second code for the second different processor type comprises converting the at least portion of source into High Level Shader Language (“

HLSL”

) code for execution on a Graphical Processing Unit (“

GPU”

).

6. The method as recited in claim 1, further comprising:

analyzing the second code to create a mapping between C++ extended for parallel environments array buffers and corresponding High Level Shader Language (“

HLSL”

) buffer variables; and

wherein

using the defined level of indirection to bind the logical buffer access to the physical buffer comprises using the mapping to bind the logical buffer access to the physical buffer access.

7. The method as recited in claim 1, wherein converting the at least one portion of source code into second code for the second different processor type, the second code defining a level of indirection between the logical buffer access and the physical buffer comprises converting the at least one portion of source code to use dynamic tags to implement the level of indirection between the logical buffer access and the physical buffer.

8. The method as recited in claim 7, wherein using the defined level of indirection to bind the logical buffer access to the physical buffer during execution of the second code comprises using the dynamic tags to multiplex logical buffer access to appropriate physical buffer access.

9. The method as recited in claim 1, wherein converting the at least one portion of source code into second code for the second different processor type, the second code defining a level of indirection between the logical buffer access and the physical buffer comprises converting the at least one portion of source code to use abstract interfaces for logical buffer access.

10. The method as recited in claim 9, wherein using the defined level of indirection to bind the logical buffer access to the physical buffer during execution of the second code comprises dynamically linking to the physical buffer access during execution.

11. At a computer system including a plurality of processors and system memory, the plurality of processors including a first processor type and a second different processor type, the runtime environment for the second different processor type disallowing aliasing of physical data buffers, a method for aliasing a buffer, the method comprising:

accessing a program, the program including source code configured for mixed execution on the first processor type and the second different processor type, the source code defining a physical buffer, the source code also including aliasing instructions for logically accessing the physical buffer through a plurality of logical views, each logical view corresponding to a subset of data in the physical buffer, at least one portion of the source code containing the aliasing instructions targeted for execution in the runtime environment for the second different processor type disallowing aliasing of physical data buffers;

converting the at least one portion of source code into second code for the second different processor type, the second code defining dynamic tags that provide a level of indirection between the logical buffer access and the physical buffer access;

analyzing the second code to create a mapping between the logical buffer access and the physical buffer access;

configuring execution of the second code within the runtime environment of the second different processor type to bind logical buffer access to the physical buffer using dynamic tags; and

using the dynamic tags to multiplex the logical buffer access to the physical buffer during execution of the second code.

12. The method as recited in claim 11, wherein accessing a program comprises accessing a C++ extended for parallel environments program.

13. The method as recited in claim 12, wherein converting the at least one portion of source code into second code for the second different processor type comprises converting the at least portion of source into High Level Shader Language (“

HLSL”

) code for execution on a Graphical Processing Unit (“

GPU”

).

14. The method as recited in claim 11, wherein accessing a program comprises accessing a program configured for mixed execution in a Central Processing Unit (“

CPU”

) runtime and a Graphical Processing Unit (“

GPU”

) runtime.

15. The method as recited in claim 11, wherein accessing a program comprises accessing a program that includes instructions for logically accessing one of:

Random Access Memory (“

RAM”

) and virtual memory on a disk.

16. At a computer system including a plurality of processors and system memory, the plurality of processors including a first processor type and a second different processor type, the runtime environment for the second different processor type disallowing aliasing of physical data buffers, a method for aliasing a buffer, the method comprising:

accessing a program, the program including source code configured for mixed execution on the first processor type and the second different processor type, the source code defining a physical buffer, the source code also including aliasing instructions for logically accessing the physical buffer through a plurality of logical views, each logical view corresponding to a subset of data in the physical buffer, at least one portion of the source code containing the aliasing instructions targeted for execution in the runtime environment for the second different processor type disallowing aliasing of physical data buffers;

converting the at least one portion of source code into second code for the second different processor type, the second code defining an abstract interface that provides a level of indirection between the logical buffer access and the physical buffer access;

configuring execution of the second code within the runtime environment of the second different processor type to bind logical buffer access to the physical buffer using a concrete implementation of the defined abstract interface; and

dynamically linking the abstract interface to the concrete implementation during execution of the second code to facilitate physical buffer access.

17. The method as recited in claim 16, wherein accessing a program comprises accessing a C++ extended for parallel environments program.

18. The method as recited in claim 17, wherein converting the at least one portion of source code into second code for the second different processor type comprises converting the at least portion of source into High Level Shader Language (“

HLSL”

) code for execution on a Graphical Processing Unit (“

GPU”

).

19. The method as recited in claim 16, wherein accessing a program comprises accessing a program configured for mixed execution in a Central Processing Unit (“

CPU”

) runtime and a Graphical Processing Unit (“

GPU”

) runtime.

20. The method as recited in claim 16, wherein accessing a program comprises accessing a program that includes instructions for logically accessing one of:

Random Access Memory (“

RAM”

) and virtual memory on a disk.