Selective posted data error detection based on history

• US 8,990,641 B2
• Filed: 11/16/2012
• Issued: 03/24/2015
• Est. Priority Date: 11/16/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gollub, Marc A., Goodman, Benjiman L., Kashyap, Sujatha, Retter, Eric E., Tschang, Yuen C.
• Primary Examiner(s): LE, DIEU MINH T
• Application Number:
  US13/679,593
• Publication Number:
  US 20140143612A1
• Time in Patent Office: 858 Days
• Field of Search: 714/48, 714/49, 714/54, 714/47.1
• US Class Current: 714/48
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00

Abstract

In a data processing system, a selection is made, based at least on addresses of previously detected errors in a memory subsystem, between at least a first timing and a second timing of data transmission with respect to completion of error detection processing on a target memory block of the memory access request. In response to receipt of the memory access request and selection of the first timing, data from the target memory block is transmitted to a requestor prior to completion of error detection processing on the target memory block. In response to receipt of the memory access request and selection of the second timing, data from the target memory block is transmitted to the requestor after and in response to completion of error detection processing on the target memory block.

Claims

1. A memory subsystem of a data processing system, comprising:

an error detection circuit; and

control logic coupled to system memory, wherein the control logic selects, based at least on addresses of previously detected errors in a memory subsystem, between at least a first timing and a second timing of data transmission with respect to completion of error detection processing by the error detection circuit on a target memory block of a memory access request, wherein the control logic, responsive to receipt of the memory access request and selection of the first timing, causes the memory subsystem to transmit data from the target memory block to a requestor prior to completion of error detection processing on the target memory block by the error detection circuit, and wherein the control logic, responsive to receipt of the memory access request and selection of the second timing, causes the memory subsystem to transmit data from the target memory block to the requestor after and in response to completion of error detection processing on the target memory block by the error detection circuit.

2. The memory subsystem of claim 1, wherein the control logic further selects between the first timing and the second timing based on an access type of a memory access request.

3. The memory subsystem of claim 2, wherein the control logic selects the first timing for the memory access request based on the memory access being one of a set including a demand data load request generated by execution of a load-type instruction and a data prefetch request.

4. The memory subsystem of claim 1, wherein:

the memory system includes a plurality of entries each recording a respective error history for one of a plurality of groups of addresses; and

the control logic selects the second timing in response to the error history for a particular one of the plurality of group of addresses including a target address of the target memory block satisfying an error threshold.

5. The memory subsystem of claim 1, wherein:

the memory system includes a plurality of entries each recording a respective error history for one of a plurality of groups of addresses; and

the control logic selects the second timing in response to the error history for a particular one of the plurality of group of addresses including a target address of the target memory block indicating an uncorrectable error.

6. The memory subsystem of claim 1, wherein the memory subsystem sends, in association with the target memory block, a posted status indicator of a timing of data transmission with respect to completion of error detection processing on the target memory block.

7. The memory subsystem of claim 1, wherein the memory subsystem, in response to receipt of the memory access request and selection of the first timing, transmits a data error indicator indicating whether or not the target memory block has a data error.

8. The memory subsystem of claim 7, wherein:

the memory subsystem transmits granules of the target memory block at intervals and transmits the data error indicator with one of the granules other than a first granule.

9. The memory subsystem of claim 1, wherein the error detection circuit employs a same error detection processing when the first timing is selected and when the second timing is selected.

10. The memory subsystem of claim 9, wherein the error detection circuit employs error correction code (ECC) error detection processing when the first timing is selected and when the second timing is selected.

11. A data processing system comprising:

the memory subsystem of claim 7; and

a processor core coupled to the memory subsystem, wherein the processor core includes the requestor.

12. The data processing system of claim 11, wherein the processor core handles the target memory block based on a timing indicated by the posted status indicator.

13. The data processing system of claim 11, wherein the processor core includes:

an execution unit that speculatively finishes execution of one or more instructions that are dependent on the target memory block prior to receipt of the data error indicator; and

completion logic that completes the one or more instructions in response to the data error indicator.

14. The data processing system of claim 11, wherein the processor core, in response to the data error indicator indicating an error in the target memory block, reissues the memory access request with the first timing disabled.

15. A design structure tangibly embodied in a non-transitory machine-readable storage medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

a memory subsystem of a data processing system, including;

an error detection circuit; and

control logic coupled to system memory, wherein the control logic selects, based at least on addresses of previously detected errors in a memory subsystem, between at least a first timing and a second timing of data transmission with respect to completion of error detection processing by the error detection circuit on a target memory block of a memory access request, wherein the control logic, responsive to receipt of the memory access request and selection of the first timing, causes the memory subsystem to transmit data from the target memory block to a requestor prior to completion of error detection processing on the target memory block by the error detection circuit, and wherein the control logic, responsive to receipt of the memory access request and selection of the second timing, causes the memory subsystem to transmit data from the target memory block to the requestor after and in response to completion of error detection processing on the target memory block by the error detection circuit.

16. The design structure of claim 15, wherein the design structure comprises a hardware description language (HDL) design structure.

17. The design structure of claim 15, wherein the control logic further selects between the first timing and the second timing based on an access type of a memory access request.

18. The design structure of claim 17, wherein the control logic selects the first timing for the memory access request based on the memory access being one of a set including a demand data load request generated by execution of a load-type instruction and a data prefetch request.

19. The design structure of claim 15, wherein:

the memory system includes a plurality of entries each recording a respective error history for one of a plurality of groups of addresses; and

the control logic selects the second timing in response to the error history for a particular one of the plurality of group of addresses including a target address of the target memory block satisfying an error threshold.

20. The design structure of claim 15, wherein:

the memory system includes a plurality of entries each recording a respective error history for one of a plurality of groups of addresses; and

the control logic selects the second timing in response to the error history for a particular one of the plurality of group of addresses including a target address of the target memory block indicating an uncorrectable error.

21. The design structure of claim 20, wherein:

the memory subsystem transmits granules of the target memory block at intervals and transmits the data error indicator with one of the granules other than a first granule.

22. The design structure of claim 15, wherein the error detection circuit employs a same error detection processing when the first timing is selected and when the second timing is selected.

23. The design structure of claim 22, wherein the error detection circuit employs error correction code (ECC) error detection processing when the first timing is selected and when the second timing is selected.