Selective masking for error correction

• US 8,990,657 B2
• Filed: 06/14/2011
• Issued: 03/24/2015
• Est. Priority Date: 06/14/2011
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Moyer, William C.
• Primary Examiner(s): Blair, April Y
• Assistant Examiner(s): NGUYEN, THIEN DANG
• Application Number:
  US13/159,878
• Publication Number:
  US 20120324312A1
• Time in Patent Office: 1,379 Days
• Field of Search: 714/763, 714/E11.034
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: H03M 13/13 Linear codes

Abstract

Error correction code (ECC) checkbits are generated for each write access to a memory address based on both the data to be written (the write data) and the memory address. The data processing device employs multiple-mapped or multi-port memory, whereby different memory addresses can be associated with the same memory location. To generate the ECC checkbits the data processing device selects a mask for each write access based on the write address and determines the ECC checkbits based on the write data, the write address, and the mask.

Claims

1. In a data processing device comprising a processor unit coupled to a memory, a method comprising:

receiving a memory access request comprising a memory address and data;

determining a mask based on the memory address; and

determining error correction code (ECC) checkbits based on the memory access request and based on the mask, wherein the mask prevents any memory address mismatch bits of the memory access request from impacting the ECC checkbits, wherein the memory address mismatch bits are differences at particular bit locations of different addresses associated with a multiple-mapped memory location.

2. The method of claim 1, wherein:

determining the ECC checkbits comprises combining a plurality of address bits of the memory address to determine the ECC checkbits; and

determining the mask comprises;

in response to the memory address being one of a first set of addresses, selecting the mask such that the ECC checkbits are based on the state of a selected one of the plurality of address bits; and

in response to the memory address being one of a second set of addresses, selecting the mask such that the ECC checkbits are not based on the state of the selected one of the plurality of address bits.

3. The method of claim 2, wherein combining the plurality of address bits comprises combining the plurality of address bits according to an exclusive-or operation.

4. The method of claim 1, wherein determining the ECC checkbits comprises:

applying the mask to the memory address according to a first logical operation to determine a first set of bits;

combining the first set of bits according to a second logical operation to determine a second set of bits; and

determining the ECC checkbits based on the second set of bits.

5. The method of claim 4, wherein the data comprises a set of data bits, and wherein determining the ECC checkbits comprises:

combining the set of data bits according to a third logical operation to determine a third set of bits; and

combining the second set of bits and the third set of bits according to a fourth logical operation to determine the ECC checkbits.

6. The method of claim 1, wherein the memory address comprises a set of memory address bits, and wherein determining the ECC checkbits comprises:

combining the set of memory address bits according to first logical operation to determine a first set of bits;

combining the mask with the first set of bits to determine a second set of bits; and

determining the ECC checkbits based on the second set of bits.

7. The method of claim 6, wherein the data comprises a set of data bits, and wherein determining the ECC checkbits comprises:

combining the set of data bits according to a third logical operation to determine a third set of bits; and

combining the second set of bits and the third set of bits according to a fourth logical operation to determine the ECC checkbits.

20. The method of claim 1, wherein determining the mask comprises looking up the mask in a stored table based on the memory address.

8. A method, comprising:

generating at a source module a write access comprising a memory address and data;

determining at the source module a mask based on the memory address;

determining at the source module error correction code (ECC) checkbits based on the memory access request and based on the mask, wherein the mask prevents any memory address mismatch bits of the memory access request from impacting the ECC checkbits, wherein the memory address mismatch bits are differences at particular bit locations of different addresses associated with a multiple-mapped memory location;

providing the data and ECC checkbits via an interconnect for storage at a memory;

receiving the data and the ECC checkbits from the memory at a requesting module via the interconnect in response to a read access; and

performing at the requesting module error detection based on the ECC checkbits.

9. The method of claim 8, wherein determining the mask comprises:

in response to the memory address being a first address, selecting the mask such that the ECC checkbits are based on a first set of address bits of the memory address; and

in response to the memory address being a second address, selecting the mask such that the ECC checkbits are based on a second set of address bits of the memory address, the first set of address bits different from the second set of address bits.

10. The method of claim 8, wherein determining the ECC checkbits comprises:

applying the mask to the memory address according to a first logical operation to determine a first set of bits;

combining the first set of bits according to a second logical operation to determine a second set of bits; and

determining the ECC checkbits based on the second set of bits.

11. The method of claim 10, wherein the data comprises a set of data bits, and wherein determining the ECC checkbits comprises:

combining the set of data bits according to a third logical operation to determine a third set of bits; and

combining the second set of bits and the third set of bits according to a fourth logical operation to determine the ECC checkbits.

12. The method of claim 8, wherein the memory address comprises a set of memory bits, and wherein determining the ECC checkbits comprises:

combining the set of memory bits according to first logical operation to determine a first set of bits;

combining the mask with the first set of bits to determine a second set of bits; and

determining the ECC checkbits based on the second set of bits.

13. The method of claim 12, wherein the data comprises a set of data bits, and wherein determining the ECC checkbits comprises:

combining the set of data bits according to a third logical operation to determine a third set of bits; and

combining the second set of bits and the third set of bits according to a fourth logical operation to determine the ECC checkbits.

14. The method of claim 8, wherein determining the mask comprises looking up the mask in a stored table based on the memory address.

15. A device, comprising:

a mask module to determine a mask based on a received memory address associated with a memory access request; and

an ECC module to generate ECC checkbits for the memory access request based on the memory address and the mask, wherein the mask prevents any memory address mismatch bits of the memory access request from impacting the ECC checkbits, wherein the memory address mismatch bits of the memory address are bit locations of the memory address that can vary from a different memory address that accesses a same location as the memory address.

16. The device of claim 15, wherein:

the ECC module is to combine a plurality of address bits of the memory address to determine the ECC checkbits; and

the mask module is to;

in response to the memory address being one of a first set of addresses, select a mask such that the ECC checkbits are based on the state of a selected one of the plurality of address bits; and

in response to the memory address being one of a second set of addresses, select a mask such that the ECC checkbits are not based on the state of the selected one of the plurality of address bits.

17. The device of claim 15 further comprising a memory comprising a plurality of memory locations.

18. The device of claim 15, wherein the ECC module comprises:

a first logic module to combine the mask and the memory address according to a first logical operation to determine a first set of bits;

a second logic module to combine the first set of bits according to a second logical operation to determine a second set of bits; and

a third logic module to determine the ECC checkbits based on the second set of bits.

19. The device of claim 15, wherein the memory address comprises a set of memory bits, and wherein the ECC module comprises:

a first logic module to combine the set of memory bits according to first logical operation to determine a first set of bits;

a second logic module to combine the mask with the first set of bits to determine a second set of bits; and

a third logic module to determine the ECC checkbits based on the second set of bits.