Data processing system having end-to-end error correction and method therefor

• US 8,990,660 B2
• Filed: 09/13/2010
• Issued: 03/24/2015
• Est. Priority Date: 09/13/2010
• Status: Expired due to Fees

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Moyer, William C.
• Primary Examiner(s): Knapp, Justin R
• Application Number:
  US12/880,352
• Publication Number:
  US 20120066567A1
• Time in Patent Office: 1,653 Days
• Field of Search: None
• US Class Current: 714/774
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems

Abstract

In a data processing system having a plurality of error coding function circuitries, a method includes receiving an address which indicates a first storage location for storing a first data value; using a first portion of the address to select one of the plurality of error coding function circuitries as a selected error coding function circuitry; and using the selected error coding function circuitry to generate a first checkbit value, wherein the selected error coding function circuitry uses the first data value to generate the first checkbit value. When the first portion of the address has a first value, a first one of the plurality of error coding function circuitries is selected as the selected error coding function circuitry. When the first portion of the address has a second value, a second one of the plurality of error coding function circuitries is selected as the selected error coding function circuitry.

Claims

1. In a data processing system having a plurality of error coding function circuitries, each implementing a different coding function, a method for generating a checkbit value, the method comprising:

receiving an address which indicates a first storage location for storing a first data value;

using a first portion of the address to select one of the plurality of error coding function circuitries as a selected error coding function circuitry, wherein;

when the first portion of the address has a first value, selecting a first one of the plurality of error coding function circuitries as the selected error coding function circuitry, and

when the first portion of the address has a second value, different from the first value, selecting a second one of the plurality of error coding function circuitries as the selected error coding function circuitry; and

using the selected error coding function circuitry to generate a first checkbit value, wherein the selected error coding function circuitry uses the first data value to generate the first checkbit value.

2. The method of claim 1, wherein the selected error coding function circuitry uses the first data value and a second portion of the address to generate the first checkbit value.

3. The method of claim 2, wherein the first portion of the address is further characterized as a more significant portion of the address than the second portion of the address.

4. The method of claim 2, wherein the second portion of the address does not include the first portion of the address.

5. The method of claim 1, further comprising:

storing the first data value and the first checkbit value.

6. The method of claim 5, further comprising:

receiving a second address which indicates a second storage location for storing a second data value;

using a first portion of the second address to select another one of the plurality of error coding function circuitries as a second selected error coding function circuitry;

using the second selected error coding function circuitry to generate a second checkbit value, wherein the second selected error coding function circuitry uses the second data value to generate the second checkbit value;

storing the second data value and the second checkbit value;

accessing the stored first data value, first checkbit value, second data value, and second checkbit value;

transforming the first checkbit value and the second checkbit value into a third checkbit value which has a granularity to cover both the first and the second data value; and

storing the first data value concatenated with the second data value and the third checkbit value in a third storage location.

7. The method of claim 6, further comprising:

transferring the first data value concatenated with the second data value over a system interconnect and using the third checkbit value to perform end to end error detection of the first data value concatenated with the second data value.

8. The method of claim 6, wherein the step of transforming comprises:

performing a bit-wise exclusive OR of the first checkbit value with the second checkbit value to obtain the third checkbit value.

9. The method of claim 6, wherein the step of transforming comprises:

performing a bit-wise exclusive OR of the first checkbit value with the second checkbit value to obtain a fourth checkbit value based on the first data value concatenated with the second data value;

providing a second portion of the address to address error coding function circuitry to generate a fifth checkbit value based on the second portion of the address; and

performing a bit-wise exclusive OR of the fourth checkbit value with the fifth checkbit value to obtain the third checkbit value.

10. In a data processing system having a processor and a memory coupled to the processor via a system interconnect, a method comprising:

accessing a cache of the processor to access a first storage location and an adjacent second storage location, wherein the first storage location comprises a first data value and a first checkbit value corresponding to the first data value and the second storage location comprises a second data value and a second checkbit value corresponding to the second data value;

transforming the first checkbit value and the second checkbit value into a third checkbit value which has a granularity to cover the first data value combined with the second data value wherein transforms includes;

performing a bit-wise XOR of the first checkbit value with the second checkbit value to obtain a fourth checkbit value based on the first data value concatenated with the second data value;

providing a second portion of an address to address error coding function circuitry to generate a fifth checkbit value based on the second portion address; and

performing a bit-wise exclusive OR of the fourth checkbit value with the fifth checkbit value to obtain the third checkbit value; and

storing the first data value concatenated with the second data value and the third checkbit value in a storage location of the memory.

11. The method of claim 10, further comprising:

transferring the first data value concatenated with the second data value over the system interconnect from the memory to the processor; and

using the third checkbit value to perform end to end error detection of the first data value concatenated with the second data value.