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Chip stack with electrically insulating walls

  • US 8,993,379 B2
  • Filed: 08/15/2013
  • Issued: 03/31/2015
  • Est. Priority Date: 01/21/2013
  • Status: Active Grant
First Claim
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1. A method of forming a chip stack, comprising:

  • arraying solder pads along a plane of a major surface of a substrate, the solder pads each having an outer surface disposed outwardly from a conductor and above insulators and an inner surface recessed from the outer surface and disposed in contact with the conductor; and

    forming walls of electrically insulating material between adjacent ones of the solder pads such that the walls extend from uppermost surfaces of the insulators and are displaced from each of the adjacent ones of the solder pads.

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