Structure and method for 3D IC package

• US 8,993,380 B2
• Filed: 03/08/2013
• Issued: 03/31/2015
• Est. Priority Date: 03/08/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hou, Shang-Yun, Yeh, Der-Chyang, Jeng, Shin-Puu, Yu, Chen-Hua
• Primary Examiner(s): Abdelaziez, Yasser A
• Application Number:
  US13/791,305
• Publication Number:
  US 20140252572A1
• Time in Patent Office: 753 Days
• Field of Search: 438/112, 257/666
• US Class Current: 438/112
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/1703 : Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/17181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73259 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81986 : Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
• CPC Class Codes: H01L 2224/83104 : by applying pressure, e.g. by injection
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/3142 : Sealing arrangements between parts, e.g. adhesion promotors
• CPC Class Codes: H01L 23/3157 : Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

Provided is a chip package structure and a method for forming the chip package. The method includes bonding a plurality of first dies on a carrier, encapsulating in a first molding compound the first dies on the carrier, coupling a plurality of second dies on the first dies using conductive elements, adding an underfill between the second dies and the first dies surrounding the conductive elements, and encapsulating in a second molding compound the second dies and the underfill. The chip package comprises a chip encapsulated in a molding compound, and a larger chip coupled to the first chip via conductive elements, wherein the conductive elements are encapsulated in an underfill between the chip and the larger chip without an interposer, and wherein the larger chip and the underfill are encapsulated in a second molding compound in contact with the molding compound.

Claims

1. A method of forming a chip package comprising:

bonding a plurality of first dies on a carrier;

encapsulating in a first molding compound the first dies on the carrier;

coupling a plurality of second dies on the first dies using conductive elements;

adding an underfill between the second dies and the first dies, the underfill surrounding the conductive elements;

encapsulating in a second molding compound the second dies and the underfill; and

de-bonding the carrier after the encapsulating in the second molding compound, the de-bonding exposing a surface of the plurality of first dies.

2. The method of claim 1, wherein the second dies are coupled to the first dies via the conductive elements without an interposer between the second dies and the first dies.

3. The method of claim 1, wherein the conductive elements include solder balls or bumps.

4. The method of claim 1 further comprising:

forming a redistribution layer (RDL) on the exposed surface of the plurality of first dies; and

forming an interconnect structure that provides three-dimensional fan-out on the RDL.

5. The method of claim 1, wherein the first dies are bonded on the carrier using an adhesive layer, and wherein de-bonding the carrier comprises removing the adhesive layer.

6. The method of claim 1 further comprising:

forming the first dies as repeated adjacent structures on a wafer;

separating the first dies; and

placing the first dies on the carrier with spacing between the first dies.

7. The method of claim 1 further comprising sawing the first dies encapsulated in the first molding compound with the underfill and the second dies encapsulated in the second molding compound to obtain a plurality of chip packages that have a three-dimensional fan-out structure.

8. A method of forming a chip package comprising:

adding first conductive elements on a first die;

adding second conductive elements on a second die larger than the first die;

placing the second die on the first die to couple the second conductive elements to the first conductive elements without an interposer; and

adding an underfill between the first die and the second die, wherein the underfill encapsulates the first conductive elements and the second conductive elements.

9. The method of claim 8 further comprising:

before placing the second die on the first die, bonding the first die on a carrier;

encapsulating the first die in a first molding compound on the carrier;

after placing the second die on the first die and adding the underfill between the first die and the second die, encapsulating the second die and the underfill in a second molding compound on the first molding compound; and

debonding the first die from the carrier.

10. The method of claim 8, wherein the second conductive elements are coupled to the first conductive elements via bump of solder balls placed between the second conductive elements and the first conductive elements in the underfill.

11. A method of forming a chip package, the method comprising:

encapsulating a first die in a first molding compound;

coupling a second die on the first die via conductive elements disposed between the first die and the second die without an interposer between the first die and the second die;

encapsulating the conductive elements in an underfill between the first die and the second die; and

encapsulating, in a second molding compound, the second die and the underfill on the first die.

12. The method of claim 11 further comprising placing the second molding compound in contact with the first molding compound.

13. The method of claim 11 further comprising:

placing a redistribution layer (RDL) on one side of the first die opposite to the underfill; and

placing a plurality of connectors on one side of the RDL opposite to the first die, the connectors providing a three-dimensional fan-out structure.

14. The method of claim 13 further comprising:

coupling the first die to first conductive elements;

coupling the second die to second conductive elements; and

coupling, inside the underfill, the first conductive elements to the second conductive elements.

15. The method of claim 14 further comprising:

coupling the connectors through the RDL to a combination of through vias and pads in the first die; and

coupling the through vias and pads to the first conductive elements.

16. The method of claim 11 further comprising forming a plurality of layers of stacked chip logic in the first die and the second die.

17. A method of forming a chip package comprising, the method comprising:

encapsulating a first chip in a molding compound;

coupling, via conductive elements, a second chip to the first chip, wherein the second chip is larger than the first chip;

encapsulating the conductive elements in an underfill without an interposer between the first chip and the second chip; and

encapsulating the second chip and the underfill in a second molding compound in contact with the molding compound.

18. The method of claim 17 further comprising:

forming stacked chip logic layers in the first chip;

forming through vias and pads across the stacked chips logic layers;

coupling a semiconductor substrate to the first chip; and

coupling second through vias in the semiconductor substrate to the through vias and pads.

19. The method of claim 17 further comprising:

placing one or more chip logic layers in the second chip; and

coupling a semiconductor substrate to the one or more chip logic layers.

20. The method of claim 17 further comprising:

adding first conductive elements to the first chip;

adding second conductive elements to the second chip;

encapsulating the first conductive elements and the second conductive element in the underfill; and

couple the first conductive elements and the second conductive elements via joints.

21. The method of claim 17 further comprising:

coupling a redistribution layer (RDL) to the first chip;

positioning the first chip between the underfill and the RDL;

coupling, to the RDL, an interconnect structure comprising a plurality of connectors for three-dimensional fan-out; and

positioning the RDL between the first chip and the interconnect structure.

22. The method of claim 21 further comprising:

forming in the RDL a conductive layer and a polymer layer;

coupling the conductive layer to the first chip and the interconnect structure; and

coupling the polymer layer to the conductive layer and the interconnect structure.