Semiconductor devices grown on indium-containing substrates utilizing indium depletion mechanisms

• US 8,994,071 B2
• Filed: 04/30/2010
• Issued: 03/31/2015
• Est. Priority Date: 05/05/2009
• Status: Active Grant

• Current Assignee: 3M Innovative Properties Company (3M Company)
• Original Assignee: 3M Innovative Properties Company (3M Company)
• Inventors: Miller, Thomas J., Haase, Michael A., Sun, Xiaoguang
• Primary Examiner(s): Campbell, Shaun
• Assistant Examiner(s): Gupta, Raj R
• Application Number:
  US13/264,509
• Publication Number:
  US 20120037957A1
• Time in Patent Office: 1,796 Days
• US Class Current: 257/191
• CPC Class Codes: H01L 21/02392 Phosphides
• CPC Class Codes: H01L 21/02463 Arsenides
• CPC Class Codes: H01L 21/02466 Antimonides
• CPC Class Codes: H01L 21/02469 Group 12/16 materials
• CPC Class Codes: H01L 21/0256 Selenides
• CPC Class Codes: H01L 21/02568 Chalcogenide semiconducting materials not being oxides, e.g. ternary compounds
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 33/0087 with a substrate not being a II-VI compound
• CPC Class Codes: H01L 33/08 with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body H01L27/15 takes precedence
• CPC Class Codes: H01L 33/28 containing only elements of Group II and Group VI of the Periodic Table
• CPC Class Codes: H01L 33/502 Wavelength conversion materials

Abstract

We have observed anomalous behavior of II-VI semiconductor devices grown on certain semiconductor substrates, and have determined that the anomalous behavior is likely the result of indium atoms from the substrate migrating into the II-V layers during growth. The indium can thus become an unintended dopant in one or more of the II-VI layers grown on the substrate, particularly layers that are close to the growth substrate, and can detrimentally impact device performance. We describe a variety of semiconductor constructions and techniques effective to deplete the migrating indium within a short distance in the growth layers, or to substantially prevent indium from migrating out of the substrate, or to otherwise substantially isolate functional II-VI layers from the migrating indium, so as to maintain good device performance.

Claims

1. A semiconductor construction, comprising:

a III-V semiconductor substrate that contains indium;

at least first and second II-VI semiconductor layers formed atop the III-V semiconductor substrate, the first II-VI semiconductor layer being disposed between the second II-VI semiconductor layer and the III-V semiconductor substrate; and

an interface disposed between the III-V semiconductor substrate and the first II-VI semiconductor layer;

wherein the first II-VI semiconductor layer is adapted to limit the migration of indium from the III-V semiconductor substrate to the second II-VI semiconductor layer, and the first II-VI semiconductor layer includes an n-type dopant in an amount effective to deplete indium that has migrated from the III-V semiconductor substrate.

2. The construction of claim 1, wherein the first and second II-VI semiconductor layers are included in a II-VI semiconductor layer stack, the layer stack being effective to convert light at a first wavelength λ

₁ to light at a second wavelength λ

₂.

3. The construction of claim 1 wherein the first II-VI semiconductor layer exhibits through its thickness an indium concentration gradient of at least a factor of 10.

4. The construction of claim 1, wherein the III-V semiconductor substrate comprises a base layer and a buffer layer, the buffer layer having a major surface corresponding to the interface, and the buffer layer exhibiting an abrupt depletion of indium in monolayers proximate the major surface.

5. The construction of claim 1, wherein the first II-VI semiconductor layer is a window layer.

6. The construction of claim 1, wherein the III-V semiconductor substrate comprises a base layer of indium phosphide (InP).

7. The construction of claim 6, wherein the III-V semiconductor substrate further comprises a buffer layer that contains indium (In).

8. The construction of claim 7, wherein the buffer layer comprises one or more of gallium indium arsenide (GaInAs), aluminum indium arsenide (AlInAs), and gallium indium aluminum arsenide (GaInAlAs).

9. The construction of claim 1, wherein the n-type dopant includes chlorine.

10. The construction of claim 9, wherein the chlorine has a doping density of at least 1×

10¹⁶ cm<sup>−

3</sup> in the first II-VI semiconductor layer.

11. The construction of claim 1, wherein the first II-VI semiconductor layer exhibits an indium concentration gradient of at least a factor of 10 over a portion of its thickness, the thickness portion being no more than 1 micron.

12. The construction of claim 11, wherein the thickness portion is no more than 0.6 microns.