Stacked carbon-based FETs

• US 8,994,080 B2
• Filed: 08/15/2013
• Issued: 03/31/2015
• Est. Priority Date: 05/09/2013
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Guo, Dechao, Han, Shu-Jen, Lu, Yu, Wong, Keith Kwong Hon
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): DINKE, BITEW A
• Application Number:
  US13/968,101
• Publication Number:
  US 20140332862A1
• Time in Patent Office: 593 Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/8256 the substrate being a semiconductor, using technologies not covered by one of groups H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252 and H01L21/8254 H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/1606 Graphene
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/66045 Field-effect transistors
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/7781 with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78645 with multiple gate

Abstract

Stacked transistor devices include a lower channel layer formed on a substrate; a pair of vertically aligned source regions formed over the lower channel layer, where the pair of source regions are separated by an insulator; a pair of vertically aligned drain regions formed on the lower channel layer, where the pair of drain regions are separated by an insulator; a pair of vertically aligned gate regions formed on the lower gate dielectric layer; and an upper channel layer formed over the source regions, drain regions, and gate regions.

Claims

1. A stacked transistor device, comprising:

a lower channel layer formed on a substrate;

a pair of vertically aligned source regions formed directly over the lower channel layer, said pair of source regions being separated by an insulator;

a pair of vertically aligned drain regions formed directly over the lower channel layer, said pair of drain regions being separated by an insulator;

conductive source and drain extensions, each formed in the substrate in electrical contact with a respective lower source and drain region;

a pair of vertically aligned gate regions formed on the lower gate dielectric layer; and

an upper channel layer formed over the source regions, drain regions, and gate regions.

2. The stacked transistor device of claim 1, wherein the upper and lower channel layers are carbon-based.

3. The stacked transistor device of claim 1, wherein the upper channel layer is carbon-based and the lower channel is silicon based.

4. The stacked transistor device of claim 1, further comprising:

a lower gate dielectric layer formed on the lower channel layer; and

an upper gate dielectric layer formed over the source regions, drain regions, and gate regions.

5. The stacked transistor device of claim 1, further comprising at least one conductive metal contact that extends from above the upper channel layer and contacts a source or drain extension.

6. The stacked transistor device of claim 5, wherein a conductive metal surface contact is in contact with both source regions or both drain regions to form a dual-transistor device.

7. The stacked transistor device of claim 6, wherein the conductive metal surface contact connects to both drain regions to form an inverter.

8. The stacked transistor device of claim 5, wherein the at least one conductive metal contact passes through an opening in the lower channel layer.

9. The stacked transistor device of claim 1, wherein at least one conductive metal contact that passes through an opening in the upper channel layer.

10. The stacked transistor device of claim 1, wherein at least one conductive metal contact is formed contiguously and from a same material as an upper source or drain region and passes through an opening in a respective insulator to contact a respective lower source or drain region.

11. The stacked transistor device of claim 1, wherein an upper source region and an upper drain region are each formed entirely from metal.

12. The stacked transistor device of claim 1, wherein an upper gate region material has a different work function from a lower gate region material, such that the gate regions will not interfere with one another in operation.