Stacked semiconductor nanowires with tunnel spacers

• US 8,994,081 B2
• Filed: 09/16/2013
• Issued: 03/31/2015
• Est. Priority Date: 05/14/2013
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Leobandung, Effendi
• Primary Examiner(s): Pham, Thanh V
• Application Number:
  US14/028,053
• Publication Number:
  US 20140339507A1
• Time in Patent Office: 561 Days
• Field of Search: 257/18, 257/29, 257/288
• US Class Current: 257/288
• CPC Class Codes: B82Y 15/00 Nanotechnology for interacting, sensing or actuating, e.g. quantum dots as markers in protein assays or molecular motors
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0669 Nanowires or nanotubes carbon nanotubes as material of solid-state device active part H10K85/211
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A structure is provided that includes at least one multilayered stacked semiconductor material structure located on a semiconductor substrate and at least one sacrificial gate material structure straddles a portion of the at least one multilayered stacked semiconductor structure. The at least one multilayered stacked semiconductor material structure includes alternating layers of sacrificial semiconductor material and semiconductor nanowire template material. End segments of each layer of sacrificial semiconductor material are then removed and filled with a dielectric spacer. Source/drain regions are formed from exposed sidewalls of each layer of semiconductor nanowire template material, and thereafter the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material are removed suspending each semiconductor material. A gate structure is formed within the areas previously occupied by the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material.

Claims

1. A semiconductor structure comprising:

at least one stacked semiconductor nanowire array suspended above a surface of a semiconductor substrate, wherein said at least one stacked semiconductor nanowire array includes a plurality of vertically spaced apart semiconductor nanowires;

a tunnel spacer located beneath and at end portions of each vertically spaced apart semiconductor nanowire of said at least one stacked semiconductor nanowire array, wherein a sidewall surface of each tunnel spacer is vertically coincident with a sidewall surface of each vertically spaced apart semiconductor nanowire of said at least one stacked semiconductor nanowire array;

a first gate structure located above a topmost vertically spaced apart semiconductor nanowire of said at least one stacked semiconductor nanowire array; and

a second gate structure located beneath each vertically spaced apart semiconductor nanowires of said at least one stacked semiconductor nanowire array and located between each tunnel spacer.

2. The semiconductor structure of claim 1, further comprising a source region located on one side of the first and second gate structures and having a sidewall surface in contact with a sidewall surface of each vertically spaced apart semiconductor nanowire of said least one stacked semiconductor nanowire array, and a drain region located on another side of the first and second gate structures and having a sidewall surface in contact with a sidewall surface of each vertically spaced apart semiconductor nanowire of said least one stacked semiconductor nanowire array.

3. The semiconductor structure of claim 1, further comprising a planarized dielectric material located above the source region and the drain region, wherein a dielectric spacer separates the planarized dielectric material located above the source region from a sidewall surface of the first gate structure, and wherein another dielectric spacer separates the planarized dielectric material located above the drain region from another sidewall surface of the first gate structure.

4. The semiconductor structure of claim 3, wherein an upper surface of the planarized dielectric material located above both the source region and the drain region is coplanar with an upper surface of the first gate structure.

5. The semiconductor structure of claim 1, wherein said first gate structure comprises a U-shaped gate dielectric having a bottommost portion in direct contact with an upper surface of the topmost vertically spaced apart semiconductor nanowire and a gate conductor located on the U-shaped gate dielectric.

6. The semiconductor structure of claim 5, wherein said U-shaped gate dielectric comprises a dielectric material having a dielectric constant of greater than silicon oxide.

7. The semiconductor structure of claim 1, wherein said second gate structure comprises a gate dielectric that surrounds a gate conductor.

8. The semiconductor structure of claim 7, wherein said gate dielectric comprises a dielectric material having a dielectric constant of greater than silicon oxide.

9. The semiconductor structure of claim 7, wherein a sidewall portion of the gate dielectric of each second gate structure contacts a sidewall surface of each tunnel spacer.

10. The semiconductor structure of claim 1, wherein each vertically spaced apart semiconductor nanowire comprises single crystal silicon.