Shielded gate trench MOS with improved source pickup layout

• US 8,994,101 B2
• Filed: 04/18/2013
• Issued: 03/31/2015
• Est. Priority Date: 03/11/2010
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Chang, Hong, Su, Yi, Li, Wenjun, Weng, Limin, Chen, Gary, Kim, Jongoh, Chen, John
• Primary Examiner(s): Menz, Laura
• Assistant Examiner(s): Malek, Maliheh
• Application Number:
  US13/865,941
• Publication Number:
  US 20130228860A1
• Time in Patent Office: 712 Days
• Field of Search: 257/302, 257330-334, 257/341, 257/E29.257, 257/E27.091, 257/E29.201, 257/E29.261, 257/E29.262, 257/E21.585, 257/E21.655, 438/242, 438/259, 438/270, 438430-432
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.

Claims

1. A semiconductor device comprising:

a semiconductor layer;

a plurality of trenches formed in the semiconductor layer, the plurality of trenches include active gate trenches located in an active area, gate runner/termination trenches and source pickup trenches located in a termination area outside the active area wherein a first conductive region is located at a bottom portion of the active gate, gate runner/termination and source pickup trenches and a second conductive region is located at a top portion of the active gate and gate runner/termination trenches, and wherein the first and second conductive regions are separated by an intermediate dielectric region;

a first electrical contact connected to the second conductive regions;

a second electrical contact connected to the first conductive region of the source pickup trenches located in the termination area, wherein the top of the first conductive region is etched back deeply throughout the device and the second electrical contact is a deep contact to the first conductive region; and

a source metal region connected to the second electrical contact and a gate metal region connected to the first electrical contact.

2. The semiconductor device of claim 1 wherein the source pickup trench is located between two adjacent active areas.

3. The semiconductor device of claim 2, wherein the source pickup trench is surrounded by gate runner/termination trenches.

7. The semiconductor device of claim 1 wherein the gate runner/termination trenches are wider than the active gate trenches and the source pickup trenches.

4. A semiconductor device comprising:

a semiconductor layer;

a plurality of trenches formed in the semiconductor layer, the plurality of trenches include active gate trenches located in an active area, gate runner/termination trenches and source pickup trenches located in a termination area outside the active area wherein a first conductive region is located at a bottom portion of the active gate, gate runner/termination and source pickup trenches and a second conductive region is located at a top portion of the active gate and gate runner/termination trenches, and wherein the first and second conductive regions are separated by an intermediate dielectric region;

a first electrical contact connected to the second conductive regions;

a second electrical contact connected to the first conductive region of the source pickup trenches located in the termination area;

a source metal region connected to the second electrical contact and a gate metal region connected to the first electrical contact,

wherein the gate runner/termination trench is asymmetrical, wherein the oxide on a first sidewall of the gate runner/termination trench is thicker than the oxide on the second sidewall of the gate runner/termination trench, the first sidewall being closer to the termination area.

5. The semiconductor device of claim 4 wherein the gate runner/termination trenches are wider than the active gate trenches and the source pickup trenches.

6. A semiconductor device comprising:

a semiconductor layer;

a plurality of trenches formed in the semiconductor layer, the plurality of trenches include active gate trenches located in an active area, gate runner/termination trenches and source pickup trenches located in a termination area outside the active area wherein a first conductive region is located at a bottom portion of the active gate, gate runner/termination and source pickup trenches and a second conductive region is located at a top portion of the active gate and gate runner/termination trenches, and wherein the first and second conductive regions are separated by an intermediate dielectric region;

a first electrical contact connected to the second conductive regions;

a second electrical contact connected to the first conductive region of the source pickup trenches located in the termination area;

a source metal region connected to the second electrical contact and a gate metal region connected to the first electrical contact; and

a gate pickup trench extending from the gate runner/termination trenches, wherein the oxide around the second conductive region in the gate pickup trench is thicker than the oxide at the bottom of the gate pickup trench.