Semiconductor integrated circuit device

• US 8,994,111 B2
• Filed: 03/11/2014
• Issued: 03/31/2015
• Est. Priority Date: 09/16/2011
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Usami, Shiro
• Primary Examiner(s): TOBERGTE, NICHOLAS J
• Application Number:
  US14/205,022
• Publication Number:
  US 20140191368A1
• Time in Patent Office: 385 Days
• Field of Search: 257/355
• US Class Current: 257/355
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements
• CPC Class Codes: H01L 27/0262 including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/0288 using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
• CPC Class Codes: H01L 27/0292 using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/87 Thyristor diodes, e.g. Shockley diodes, break-over diodes

Abstract

Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring connected to a signal terminal. Diffusion regions are separated in a whole part or one part of a range in a Y direction. That is, under first wiring, diffusion regions are only formed in parts opposed to diffusion regions formed under the second wiring and third wiring connected to a power supply terminal or a ground terminal, and a diffusion region is not formed in a central part in an X direction. Therefore, terminal capacity of the signal terminal can be reduced without causing ESD resistance to be reduced, in an ESD protection circuit with the signal terminal.

Claims

1. A semiconductor integrated circuit device having an ESD (Electro Static Discharge) protection circuit, wherein:

the ESD protection circuit comprises;

a first wiring extending in a first direction and electrically connected to a first terminal;

a second wiring and a third wiring extending in the first direction, electrically connected to a power supply terminal or a ground terminal, and disposed on both sides of the first wiring respectively;

a first diffusion region and a second diffusion region that are connected to and formed under the first wiring, having a same first conductivity type with each other, disposed between the second wiring and the third wiring, in a second direction perpendicular to the first direction, the first and second diffusion regions being at least partially separated from each other;

a third diffusion region connected to and formed under the second wiring, having a second conductivity type, and disposed so as to be opposed to the first diffusion region in the second direction; and

a fourth diffusion region connected to and formed under the third wiring, having the second conductivity type, and disposed so as to be opposed to the second diffusion region in the second direction,

the third diffusion region, the first diffusion region, the second diffusion region and the fourth diffusion region are disposed in this order in the second direction, and

the first conductivity type is different from the second conductivity type.

2. The semiconductor integrated circuit device according to claim 1, wherein

each of the first, second, third, and fourth diffusion regions has a rectangular shape of which length in the first direction are greater than a length in the second direction.

3. The semiconductor integrated circuit device according to claim 1, wherein

a length of each of the first and second diffusion regions in the second direction is smaller than a length of each of the third and fourth diffusion regions in the second direction.

4. The semiconductor integrated circuit device according to claim 1, wherein

the third and fourth diffusion regions are connected to each other through a diffusion region.

5. The semiconductor integrated circuit device according to claim 1, wherein:

in an area including the first diffusion region and the third diffusion region opposed to each other, a space between the first wiring and the second wiring is larger than a space between the first diffusion region and the third diffusion region, and

in an area including the second diffusion region and the fourth diffusion region opposed to each other, a space between the first wiring and the third wiring is larger than a space between the second diffusion region and the fourth diffusion region.

6. The semiconductor integrated circuit device according to claim 1, wherein:

in an area including the first diffusion region and the third diffusion region opposed to each other, the third diffusion region protrudes toward the first diffusion region from the second wiring in a planar view, and

in an area including the second diffusion region and the fourth diffusion region opposed to each other, the fourth diffusion region protrudes toward the second diffusion region from the third wiring in a planar view.

7. The semiconductor integrated circuit device according to claim 1, wherein

the second wiring and third wiring are electrically connected to the power supply terminal.

8. The semiconductor integrated circuit device according to claim 7, wherein:

the first conductivity type is a P type, and the second conductivity type is an N type, and

the ESD protection circuit is a diode type having the first terminal as an anode and the power supply terminal as a cathode.

9. The semiconductor integrated circuit device according to claim 1, wherein

the second wiring and third wiring are connected to the ground terminal.

10. The semiconductor integrated circuit device according to claim 9, wherein:

the first conductivity type is an N type, and the second conductivity type is a P type, and

the ESD protection circuit is a diode type having the ground terminal as an anode and the first terminal as a cathode.

11. The semiconductor integrated circuit device according to claim 1, wherein

the first and second diffusion regions are separated from each other.

12. The semiconductor integrated circuit device according to claim 4, wherein

each of the first, second, third, and fourth diffusion regions has a rectangular shape of which length in the first direction are greater than a length in the second direction.

13. The semiconductor integrated circuit device according to claim 4, wherein

a length of each of the first and second diffusion regions in the second direction is smaller than a length of each of the third and fourth diffusion regions in the second direction.

14. The semiconductor integrated circuit device according to claim 4, wherein:

in an area including the first diffusion region and the third diffusion region opposed to each other, a space between the first wiring and the second wiring is larger than a space between the first diffusion region and the third diffusion region, and

in an area including the second diffusion region and the fourth diffusion region opposed to each other, a space between the first wiring and the third wiring is larger than a space between the second diffusion region and the fourth diffusion region.

15. The semiconductor integrated circuit device according to claim 4, wherein:

in an area including the first diffusion region and the third diffusion region opposed to each other, the third diffusion region protrudes toward the first diffusion region from the second wiring in a planar view, and

in an area including the second diffusion region and the fourth diffusion region opposed to each other, the fourth diffusion region protrudes toward the second diffusion region from the third wiring in a planar view.

16. The semiconductor integrated circuit device according to claim 4, wherein

the second wiring and third wiring are electrically connected to the power supply terminal.

17. The semiconductor integrated circuit device according to claim 16, wherein:

the first conductivity type is a P type, and the second conductivity type is an N type, and

the ESD protection circuit is a diode type having the first terminal as an anode and the power supply terminal as a cathode.

18. The semiconductor integrated circuit device according to claim 4, wherein

the third and fourth diffusion regions are connected to each other through two diffusion regions so as to surround the first and second diffusion regions.

19. The semiconductor integrated circuit device according to claim 1, wherein:

the first and second diffusion regions are connected to the first wiring via first contacts,

the third diffusion region is connected the second wiring via second contacts, and

the fourth diffusion region is connected to the third wiring via third contacts.