Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices

• US 8,994,163 B2
• Filed: 01/24/2013
• Issued: 03/31/2015
• Est. Priority Date: 06/15/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pratt, David S.
• Primary Examiner(s): Parekh, Nitin
• Application Number:
  US13/749,521
• Publication Number:
  US 20130134605A1
• Time in Patent Office: 796 Days
• Field of Search: 257/686, 257/777, 257/723
• US Class Current: 257/686
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto when forming bonding pads H01L24/03; when forming bump connectors H01L24/11; when forming layer connectors H01L24/27
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/11002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16148 : the bump connector connecting to a bonding area protruding from the surface
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/812 : Applying energy for connecting
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/83005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/06596 : Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/48 : Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

Stacked semiconductor devices, semiconductor assemblies, methods of manufacturing stacked semiconductor devices, and methods of manufacturing semiconductor assemblies. One embodiment of a semiconductor assembly comprises a thinned semiconductor wafer having an active side releaseably attached to a temporary carrier, a back side, and a plurality of first dies at the active side. The individual first dies have an integrated circuit, first through die interconnects electrically connected to the integrated circuit, and interconnect contacts exposed at the back side of the wafer. The assembly further includes a plurality of separate second dies attached to corresponding first dies on a front side, wherein the individual second dies have integrated circuits, through die interconnects electrically connected to the integrated circuits and contact points at a back side, and wherein the individual second dies have a thickness of approximately less than 100 microns.

Claims

1. A semiconductor assembly, comprising:

a thinned semiconductor wafer having an active side, a back side with a back side surface opposite the active side, and a plurality of first dies arranged in a die pattern at the active side, wherein individual first dies have first mounting terminals, an integrated circuit, and first through die interconnects electrically connected to the first mounting terminals, wherein the first mounting terminals are exposed at the active side of the wafer and are electrically connected to the integrated circuit, wherein the first through die interconnects extend from the active side and extend through the back side surface such that ends of the first through die interconnects protrude from the back side surface to define interconnect contacts exposed at the back side of the wafer; and

a plurality of separate second dies spaced apart from each other and arranged in the die pattern relative to the thinned semiconductor wafer, individual second dies having a second active side electrically coupled to corresponding interconnect contacts and located at the back side of the wafer,

a second back side,

a second integrated circuit, and

a second terminal electrically coupled to the second integrated circuit on the second active side,

wherein the individual second dies have a thickness of approximately less than 150 microns.

2. The assembly of claim 1, further comprising an underfill material deposited between the first and second dies.

3. The assembly of claim 1 wherein the thickness of the plurality of second dies is substantially uniform across the thinned semiconductor wafer.

4. The assembly of claim 1 wherein the thinned semiconductor wafer has a thickness of approximately less than 100 microns.

5. The assembly of claim 1 wherein the thinned semiconductor wafer has a wafer thickness of approximately less than 50 microns and the thickness of the second die is approximately less than 50 microns.

6. The assembly of claim 1, further comprising:

a plurality of separate third dies spaced apart from each other and arranged in the die pattern relative to the thinned semiconductor wafer, individual third dies having a third active side, a third back side, a third integrated circuit, and a third terminal electrically coupled to the third integrated circuit on the third active side, wherein the third die has a thickness of approximately less than 100 microns.

7. The assembly of claim 1, further comprising underfill material between the thinned semiconductor wafer and the second dies, wherein the underfill material surrounds sections of the interconnect contacts between the thinned semiconductor wafer and the second dies.

8. The assembly of claim 1 wherein the back side surface is a polished surface that is spaced apart from the second dies to define a stand-off space filled by an underfill material.

9. The assembly of claim 1 wherein the plurality of first dies are exposed at the active side of the thinned semiconductor wafer;

and

the second active sides of the second dies face the back side of the thinned semiconductor wafer.

10. The assembly of claim 1, further comprising:

a plurality of under bump metallurgy plated pads located between and connecting the interconnect contacts of the thinned semiconductor wafer and the second terminals of the second dies, wherein the under bump metallurgy plated pads and the interconnect contacts space apart the second dies from the thinned semiconductor wafer to define a stand-off space; and

an underfill material located in the stand-off space and surrounding the interconnect contacts and the under bump metallurgy plated pads.

11. The assembly of claim 1 wherein the first dies include a redistribution layer at the active side of the thinned semiconductor wafer.

12. The assembly of claim 1 wherein

the plurality of first dies includes a plurality of known good first dies and a plurality of known bad first dies;

and

the plurality of separate second dies includes

a plurality of separated known good second dies electrically coupled to corresponding known good first dies, and

a plurality of separated known bad second dies electrically coupled to corresponding known bad first dies.

13. An intermediate stacked semiconductor assembly, comprising:

a thinned semiconductor wafer having an active side with mounting terminals, a plurality of first dies arranged in a die pattern, a back side with a back side surface, and first through die interconnects extending from the active side and end portions of the first through die interconnects extend through the back side surface of the wafer such that the end portions define interconnect contacts protruding from the back side surface;

a plurality of singulated second dies located on the back side of the thinned semiconductor wafer and electrically connected to the interconnect contacts, wherein the individual second dies are spaced apart from each other by gaps, and wherein the second dies have a first side, a second side spaced apart from the first side by a handling thickness, and a second interconnect extending from the first side to an intermediate depth in the second die such that the second interconnects are not exposed on the second side of the second dies; and

an encapsulant in the gaps.

14. The assembly of claim 13 wherein the individual second dies have a handling thickness approximately greater than 300 microns.

15. The assembly of claim 13 wherein the thinned semiconductor wafer has a final thickness approximately less than 50 microns.

16. The assembly of claim 13, further comprising an underfill material between the thinned semiconductor wafer and the second dies, wherein the underfill material surrounds ends of the first through die interconnects located between the thinned semiconductor wafer and the second dies.

17. The intermediate stacked semiconductor assembly of claim 13 wherein

the first dies include a plurality of known good first dies and a plurality of known bad first dies;

and

the second dies include a plurality of known good second dies and a plurality of known bad second dies, wherein the known good second dies are attached to corresponding known good first dies, and wherein the known bad second dies are attached to corresponding known bad first dies.

18. A semiconductor assembly, comprising:

a wafer including a plurality of known good first dies and a plurality of known bad first dies;

a plurality of separated known good second dies attached to corresponding known good first dies, and a plurality of separated known bad second dies attached to corresponding known bad first dies, wherein the known good and bad second dies are spaced apart from each other by gaps; and

an encapsulant material in the gaps.

19. The assembly of claim 18 wherein the wafer has a thickness approximately less than 100 microns.

20. The assembly of claim 18 wherein the separated known good second dies and/or the separated known bad second dies have a thickness approximately less than 100 microns.

21. The assembly of claim 18 wherein the known good first dies individually comprise a first integrated circuit electrically coupled to a first terminal and a through die interconnect, and wherein the known good second dies individually comprise a second terminal electrically coupled to a second integrated circuit and an interconnect contact point of the corresponding through die interconnect.