Multiphase transformer for a multiphase DC-DC converter

• US 8,994,344 B2
• Filed: 12/26/2012
• Issued: 03/31/2015
• Est. Priority Date: 06/30/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Schrom, Gerhard, Hazucha, Peter, Lee, Jaeseo, Karnik, Tanay, De, Vivek K., Paillet, Fabrice
• Primary Examiner(s): Tran, Thienvu
• Assistant Examiner(s): MAI, TIEN HUNG
• Application Number:
  US13/727,227
• Publication Number:
  US 20130113444A1
• Time in Patent Office: 825 Days
• Field of Search: 323/272, 323/247
• US Class Current: 323/247
• CPC Class Codes: G05F 1/468 characterised by reference voltage circuitry, e.g. soft start, remote shutdown
• CPC Class Codes: H02M 1/14 Arrangements for reducing ripples from dc input or output
• CPC Class Codes: H02M 7/068 mounted on a transformer

Abstract

A multiphase DC-DC converter is provided that includes a multiphase transformer, the multiphase transformer including a plurality of input voltage terminals and an transformer output voltage terminal, each input voltage terminal associated with a corresponding phase. Each phase is assigned to an input voltage terminal of the plurality of input voltage terminals to minimize a ripple current at the input voltage terminals of the multiphase transformer.

Claims

1. A multiphase DC-DC converter comprising:

a multiphase transformer having a plurality of input voltage terminals;

shuffle circuitry coupled to the multiphase transformer, the shuffle circuitry;

assign a first phase, to a first terminal of the plurality of input voltage terminals;

assign a second phase, to a second terminal of the plurality of input voltage terminals if a total number of number of phases is odd;

assign a third phase to the second terminal of the plurality of input voltage terminals if a total number of phases is even.

2. The multiphase DC-DC converter of claim 1 further comprises:

an output voltage terminal coupled to another output voltage terminal of another multiphase DC-DC converter; and

a capacitor coupled to the output voltage terminal.

3. The multiphase DC-DC converter of claim 2, wherein the other multiphase DC-DC converter is in parallel to the multiphase DC-DC converter.

4. The multiphase DC-DC converter of claim of 1, wherein the multiphase transformer is one of a:

multiphase transformer with cyclic cascade topology;

multiphase transformer with mixed cyclic cascade topology;

or

multiphase transformer with modified cyclic cascade topology.

5. The multiphase DC-DC converter of claim of 4, wherein the multiphase transformer with one of cyclic cascade topology, multiphase transformer with mixed cyclic cascade topology, and multiphase transformer with mixed cyclic cascade topology include two-phase transformers.

6. The multiphase DC-DC converter of claim of 5, wherein the two-phase transformers are arranged in at least two columns to reduce parasitic resistance between the two-phase transformers.

7. The multiphase DC-DC converter of claim of 4, wherein the cyclic cascade topology has an odd number of phases.

8. The multiphase DC-DC converter of claim of 4, wherein the mixed cyclic cascade topology has an even number of phases.

9. The multiphase DC-DC converter of claim of 4, wherein the modified cyclic cascade topology has an odd number of phases.

10. The multiphase DC-DC converter of claim 1, wherein the multiphase transformer comprises directly-coupled inductors with equal number of windings made on a common core.

11. The multiphase DC-DC converter of claim 10, wherein the directly-coupled inductors are integrated on a semiconductor die.

12. The multiphase DC-DC converter of claim 1, wherein the first, second, and third phases are applied with pulse width modulation (PWM).

13. An integrated circuit comprising:

a processor having multiple processing cores; and

a plurality of voltage regulators, each of which to provide a corresponding regulated power supply voltage to a corresponding processing core from among the multiple processing cores, wherein each voltage regulator comprises;

a multiphase transformer having a plurality of input voltage terminals;

shuffle circuitry coupled to the multiphase transformer, the shuffle circuitry;

assign a first phase, to a first terminal of the plurality of input voltage terminals;

assign a second phase, to a second terminal of the plurality of input voltage terminals if a total number of number of phases is odd;

assign a third phase to the second terminal of the plurality of input voltage terminals if a total number of phases is even.

14. The integrated circuit of claim of 13, wherein the multiphase transformer is one of a:

multiphase transformer with cyclic cascade topology;

multiphase transformer with mixed cyclic cascade topology;

or

multiphase transformer with modified cyclic cascade topology.

15. A method, comprising:

establishing a relationship between input phases and input terminals of a multi-phase transformer integrated on a semiconductor chip including;

assigning a first phase to a first terminal of the plurality of input terminals;

assigning a second phase to a second terminal of the plurality of input terminals if a total number of number of phases is odd;

assigning a third phase to the second terminal of the plurality of input terminals if a total number of phases is even.

16. The method of claim 15 wherein the semiconductor chip includes a processing core and the multi-phase transformer is coupled to a power supply input of the processing core.

17. The method of claim 15 wherein the established relationship helps implement any of the following:

a multiphase transformer with cyclic cascade topology;

a multiphase transformer with mixed cyclic cascade topology;

a multiphase transformer with modified cyclic cascade topology.

18. The method of claim 15 wherein the programmably establishing comprises blowing fuses within a shuffle circuit coupled between respective signal lines that transport the phases and the input terminals.