Semiconductor device and structure

• US 8,994,404 B1
• Filed: 03/12/2013
• Issued: 03/31/2015
• Est. Priority Date: 03/12/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Wurman, Zeev
• Primary Examiner(s): CRAWFORD, JASON
• Application Number:
  US13/796,930
• Time in Patent Office: 749 Days
• Field of Search: 326 37- 41, 326/47, 326/93, 326 95- 98
• US Class Current: 326/93
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H03K 19/096 Synchronous circuits, i.e. using clock signals H03K19/01728, H03K19/01855 take precedence

Abstract

A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection; the first layer includes a first clock distribution structure, the first clock distribution structure includes a first clock origin, the second layer includes a second clock distribution structure, the second clock distribution structure includes a second clock origin, and the second clock origin is feeding the first clock origin.

Claims

1. A 3D device, comprising:

a first layer comprising first transistors, said first transistors interconnected by a first layer of interconnection;

a second layer comprising second transistors, said second transistors overlaying said first layer of interconnection;

wherein said first layer comprises a first clock distribution structure, said first clock distribution structure comprising a first clock origin,

wherein said second layer comprises a second clock distribution structure, said second clock distribution structure comprises a second clock origin, and

wherein said second clock origin is feeding said first clock origin.

2. A 3D device according to claim 1,

wherein said second clock distribution structure comprises a clock tree.

3. A 3D device according to claim 1,

wherein said second clock distribution structure comprises a clock mesh.

4. A 3D device according to claim 1,

wherein said second clock distribution structure comprises at least one cross-link to connect it to said first clock distribution structure.

5. A mobile system comprising a 3D device according to claim 1.

6. A 3D device according to claim 1, further comprising:

an electronic circuit comprised by said second transistors;

wherein said first layer comprises a plurality of first flip-flops connected to form a first scan chain, and

wherein said first scan chain is connected to provide scan information to said electronic circuit.

7. A 3D device according to claim 1,

wherein said first layer comprises a first bus, said first bus interconnecting a plurality of first logic units,

wherein said second layer comprises a second bus, said second bus interconnecting a plurality of second logic units, and

wherein said first bus and said second bus are interconnected so said second logic units could communicate through said first bus with at least one of said first logic units.

8. A mobile system comprising a 3D device according to claim 1.

9. A 3D device, comprising:

a first layer comprising first transistors said first transistors interconnected by a first layer of interconnection;

a second layer comprising second transistors, said second transistors overlaying said first layer of interconnection;

an electronic circuit comprised by said second transistors;

wherein said first layer comprises a plurality of first flip-flops connected to form a first scan chain, and

wherein said first scan chain is connected to provide scan information to said electronic circuit.

10. A 3D device according to claim 9,

wherein said second layer is connected to said first layer to provide test information to said first scan chain.

11. A 3D device according to claim 9, further comprising:

a wireless communication circuit,

wherein said wireless communication circuit enables wireless testing of said device while said device is still is part of a wafer.

12. A 3D device according to claim 9,

wherein said device is designed to be tested in wafer form before said second layer has been overlaid.

13. A mobile system comprising a 3D device according to claim 9.

14. A 3D device according to claim 9,

wherein said first layer comprises a first clock distribution structure, said first clock distribution structure comprising a first clock origin,

wherein said second layer comprises a second clock distribution structure, said second clock distribution structure comprising a second clock origin, and

wherein said second clock origin is feeding said second clock origin.

15. A 3D device according to claim 9,

wherein said first layer comprises a first bus, said first bus interconnecting a plurality of first logic units,

wherein said second layer comprises a second bus, said second bus interconnecting a plurality of second logic units, and

wherein said first bus and said second bus are interconnected so said second logic units could communicate through said first bus with at least one of said first logic units.

16. A 3D device, comprising:

a first layer comprising first transistors, said first transistors interconnected by a first layer of interconnection;

a second layer comprising second transistors, said second transistors overlaying said first layer of interconnection;

wherein said first layer comprises a first bus, said first bus interconnecting a plurality of first logic units,

wherein said second layer comprises a second bus, said second bus interconnecting a plurality of second logic units, and

wherein said first bus and said second bus are interconnected so said second logic units could communicate through said first bus with at least one of said first logic units.

17. A 3D device according to claim 16,

wherein at least one of said second logic units has a plurality of connections to an external component.

18. A 3D device according to claim 16, wherein said first bus is one of the following:

i.) an Advanced Microcontroller Bus Architecture (AMBA) bus;

ii) a CoreConnect bus;

iii) a STBus;

iv.) a Wishbone bus;

v.) an Open Core Protocol (OCP) bus, or

vi.) a Virtual Component Interface (VCI) bus.

19. A 3D device according to claim 16,

wherein said first layer comprises a first clock distribution structure, said first clock distribution structure comprises a first clock origin,

wherein said second layer comprises a second clock distribution structure, said second clock distribution structure comprises a second clock origin, and

wherein said second clock origin is feeding said first clock origin.

20. A 3D device according to claim 16, further comprising:

an electronic circuit comprised by said second transistors;

wherein said first layer comprises a plurality of first flip-flops connected to form a first scan chain, and

wherein said first scan chain is connected to provide scan information to said electronic circuit.