Multiple VDD clock buffer
First Claim
Patent Images
1. A buffer circuit, comprising:
- a low voltage drive circuit operating at a first supply potential, the low voltage drive circuit coupled to receive a clock input signal at a low voltage drive circuit input terminal and directly connected to provide a clock output signal at an output node; and
a boost drive circuit operating at a second supply potential greater than the first supply potential, the boost drive circuit coupled to receive a pulse signal and provide a low impedance path between the second supply potential and the output node in response to the pulse signal to drive the output node.
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Abstract
A clock buffer circuit can include a low voltage drive circuit that receives a clock signal and provides a low voltage drive at a first power supply potential to a load. A boost drive circuit can provide a high voltage drive at a second power supply potential greater than the first power supply potential to the load. The boost drive circuit can provide the high voltage drive in response to a pulse signal generated in response to a transition of a clock input signal. A pulse generator circuit may generate the pulse signal to have a predetermined width to enable the high voltage drive until the load is charged essentially to the first power supply potential.
267 Citations
20 Claims
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1. A buffer circuit, comprising:
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a low voltage drive circuit operating at a first supply potential, the low voltage drive circuit coupled to receive a clock input signal at a low voltage drive circuit input terminal and directly connected to provide a clock output signal at an output node; and a boost drive circuit operating at a second supply potential greater than the first supply potential, the boost drive circuit coupled to receive a pulse signal and provide a low impedance path between the second supply potential and the output node in response to the pulse signal to drive the output node. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A buffer circuit, comprising:
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a low voltage drive circuit operating at a first supply potential, the low voltage drive circuit coupled to receive an input signal at a low voltage drive circuit input terminal and directly connected to provide an output signal at an output node; a boost drive circuit operating at a second supply potential greater than the first supply potential, the boost drive circuit coupled to receive a pulse signal at a boost drive circuit input terminal and provide a low impedance path between the second supply potential and the output node in response to the pulse signal to drive the output node; and a pulse generator circuit coupled to receive the input signal at a pulse generator circuit input terminal and provide the pulse signal. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification