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Multiple VDD clock buffer

  • US 8,994,415 B1
  • Filed: 03/01/2013
  • Issued: 03/31/2015
  • Est. Priority Date: 03/01/2013
  • Status: Active Grant
First Claim
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1. A buffer circuit, comprising:

  • a low voltage drive circuit operating at a first supply potential, the low voltage drive circuit coupled to receive a clock input signal at a low voltage drive circuit input terminal and directly connected to provide a clock output signal at an output node; and

    a boost drive circuit operating at a second supply potential greater than the first supply potential, the boost drive circuit coupled to receive a pulse signal and provide a low impedance path between the second supply potential and the output node in response to the pulse signal to drive the output node.

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