Period signal generation circuits

• US 8,994,428 B2
• Filed: 08/13/2013
• Issued: 03/31/2015
• Est. Priority Date: 02/07/2013
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Ham, Hyun Ju
• Primary Examiner(s): Hiltunen, Thomas J
• Application Number:
  US13/965,793
• Publication Number:
  US 20140218101A1
• Time in Patent Office: 595 Days
• Field of Search: 331/69, 331/70, 331/176
• US Class Current: 327/176
• CPC Class Codes: G05F 1/463 Sources providing an output which depends on temperature
• CPC Class Codes: H03K 3/011 Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature to maintain energy constant H03K3/015
• CPC Class Codes: H03K 3/037 Bistable circuits
• CPC Class Codes: H03K 5/05 by the use of clock signals or other time reference signals

Abstract

A period signal generation circuit including a control voltage generator and a period controller. The control voltage generator selecting one of temperature-dependent voltages to output the selected temperature-dependent voltage as a control voltage. The first and second temperature-dependent voltages varying according to a temperature and the third temperature-dependent voltage is constant regardless of variation of the temperature. The period controller configured to determine an amount of a current discharging from an internal node in response to the control voltage and outputs a periodic signal whose cycle time is determined according to a level of an internal signal induced at the internal node.

Claims

1. A period signal generation circuit, the circuit comprising:

a control voltage generator configured to select one of plurality of temperature-dependent voltages to output the selected temperature-dependent voltage as a control voltage; and

a period controller configured to determine an amount of a current discharging from an internal node in response to the control voltage and to output a periodic signal having a cycle time that is determined according to a level of an internal signal induced at the internal node, wherein the plurality of temperature-dependent voltages comprises the first and second temperature-dependent voltages varying according to a temperature and the third temperature-dependent voltage being constant regardless of the temperature.

2. The circuit of claim 1, wherein a level of the first temperature-dependent voltage increases as the temperature rises and a level of the second temperature-dependent voltage decreases as the temperature rises.

3. The circuit of claim 2, wherein the levels of the first and second temperature-dependent voltages linearly vary according to variation of the temperature.

4. The circuit of claim 2, wherein the control voltage generator includes:

a temperature-dependent voltage generator configured to generate the first to third temperature-dependent voltages;

an amplifier configured to amplify the first and second temperature-dependent voltages varying according to the temperature to generate a first amplified voltage and a second amplified voltage and configured to amplify the third temperature-dependent voltage to generate a third amplified voltage; and

a selector configured to select one the first to third amplified voltages in response to selection signals to output the selected amplified voltage as the control voltage.

5. The circuit of claim 4, wherein the selection signals are generated from an internal circuit or an external circuit.

6. The circuit of claim 4, wherein the selection signals include a first selection signal, a second selection signal and a third selection signal, the selector includes:

a first transfer gate configured to output the first amplified voltage as the control voltage in response to the first selection signal;

a second transfer gate configured to output the second amplified voltage as the control voltage in response to the second selection signal; and

a third transfer gate configured to output the third amplified voltage as the control voltage in response to the third selection signal.

7. The circuit of claim 1, wherein the period controller includes:

a discharger configured to discharge charges of the internal node in response to the control voltage;

a level detector configured to compare a level of the internal signal with a reference voltage to determine a level of the periodic signal; and

a driver configured to drive the internal node in response to the periodic signal.

8. The circuit of claim 7, wherein an amount of charges discharged through the discharger increases as a level of the control voltage increases.

9. The circuit of claim 7, wherein the level detector is configured to generate the periodic signal having a first logic level when the internal signal has a higher level than the reference voltage and to generate the periodic signal having a second logic level when the internal signal has a lower level than the reference voltage.

10. The circuit of claim 9, wherein the driver is configured to drive the internal node when the periodic signal has the second logic level.

11. The circuit of claim 7, further comprising a reset unit configured to initialize the periodic signal in response to a reset signal.