Artifact-free transitions between dual display controllers

• US 8,994,700 B2
• Filed: 03/23/2007
• Issued: 03/31/2015
• Est. Priority Date: 03/23/2006
• Status: Active Grant

• Current Assignee: One Laptop Per Child Association Inc.
• Original Assignee: One Laptop Per Child Association Inc.
• Inventors: Foster, Mark J.
• Primary Examiner(s): Ghebretinsae, Temesgh
• Assistant Examiner(s): Ketema, Benyam
• Application Number:
  US11/726,776
• Publication Number:
  US 20070222774A1
• Time in Patent Office: 2,930 Days
• Field of Search: 345 98-100, 345/204
• US Class Current: 345/204
• CPC Class Codes: G06F 3/1431 using a single graphics controller
• CPC Class Codes: G09G 2360/04 Display device controller operating with a plurality of display units
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel

Abstract

A method, system and computer program product for driving a display device by a display system is provided. The display system includes a processor, a first display controller, a second display controller and the display device. The first display controller receives display frames that are sent by the processor. The first display controller drives the display device when the processor sends new display frames. When the same display frames are continually sent by the processor, the control of the display device is switched to the second display controller, which is optimized for low-power operation. The control of the display device is switched in proximity to an input vertical synchronization (V-sync) pulse.

Claims

1. A method for driving a display device by a display system, the display system comprising the display device, a first display controller, a second display controller and a processor, the second display controller being optimized for low-power operation, the method comprising the steps of:

receiving display data from the processor, the display data being received at the first display controller;

switching control of the display device between the first display controller and the second display controller, the control of the display device being switched in proximity to a trailing edge of an input vertical synchronization (V-sync) pulse; and

refreshing the display device, the display device being refreshed by the second display controller with a clock independent of the processor and the first display controller.

2. The method of claim 1, wherein the step of switching the control of the display device comprises the step of setting a first pin of the second display controller to a low state when no new frame is written to a frame buffer of the first display controller.

3. The method of claim 2, wherein the step of setting the first pin to the low state comprises the step of performing a display load cycle, the step of performing the display load cycle comprising storing a frame into a frame buffer of the second display controller, the storing of the frame being commenced at the trailing edge of the input V-sync pulse.

4. The method of claim 1, wherein the step of switching the control of the display device comprises the step of setting a first pin of the second display controller to a high intermediate state when one or more new frames are written to a frame buffer of the first display controller, the high intermediate state of the first pin indicating an intermediate high-power recording state.

5. The method of claim 1, wherein the step of switching the control of the display device comprises the step of performing a transition between one or more video timings of the first display controller and one or more video timings of the second display controller.

6. The method of claim 5, wherein the step of performing the transition comprises synchronously re-initializing the one or more video timings of the first display controller and the second display controller, the one or more video timings being synchronously re-initialized during a blanking interval.

7. The method of claim 5, wherein the step of switching the control of the display device further comprises the step of switching a frame buffer of the second display controller from a write mode to a read mode.

8. The method of claim 5, wherein the step of switching the control of the display device further comprises the step of communicating frame timing from the second display controller to the processor, the step of communicating comprises the steps of:

setting a second pin of the second display controller to a low state at a pre-determined point prior to the V-sync pulse; and

setting the second pin to a high state during a blanking interval, the blanking interval being an interval between the trailing edge of the V-sync pulse and the start of a new active scanline.

9. The method of claim 5, wherein the step of switching the control of the display device further comprises the step of servicing one or more types of scanline interrupts, each type of scanline interrupt having a timing relative to a pre-selected scanline, each type of scanline interrupt being serviced by a third pin of the second display controller, and the type of the scanline interrupt being indicated by a fourth or more pins of the second display controller.

10. The method of claim 9, wherein the step of servicing the one or more types of scanline interrupts further comprises the step of disabling the first display controller on the basis of the type of the scanline interrupt.

11. The method of claim 9, wherein the step of servicing the one or more types of scanline interrupt further comprises the step of alerting the processor to re-initialize the one or more video timings of the first display controller synchronously with the one or more video timings of the second display controller, the re-initialization being performed on the basis of the type of the scanline interrupt.

12. The method of claim 5, wherein the step of switching the control of the display device further comprises the step of driving the second display controller to an inactive mode based on the value of the one or more registers of the second display controller.

13. The method of claim 1, wherein the step of refreshing the display device comprises the step of activating the second display controller from an inactive mode, the second display controller being activated by the processor when the processor receives an input from one or more input devices.

14. The method of claim 1, wherein the step of refreshing the display device comprises the steps of:

setting a fifth pin of the second display controller to a high state from a low state, the fifth pin being set when the processor receives an input from one or more input devices;

activating the second display controller from an inactive mode.

15. The method of claim 1, wherein the step of refreshing the display device comprises commanding the first display controller to activate one or more video outputs when one or more new frames are written to a frame buffer of the first display controller.

16. The method of claim 1, wherein the step of refreshing the display device comprises autonomously driving the display device by the second display controller when no new frame is written to a frame buffer of the first display controller.

17. A system for driving a display device by a display system, the display system comprising the display device, a first display controller, a second display controller and a processor, the second display controller being optimized for low-power operation, the system comprising:

means for communicating display data of the first display controller to the second display controller;

means for switching control of the display device between the first display controller and the second display controller, the control of the display device being switched in proximity to the trailing edge of an input vertical synchronization (V-sync) pulse; and

means for refreshing the display device, the display device being refreshed by the second display controller with a clock independent of the processor and the first display controller.

18. A non-transitory machine-readable storage medium comprising one or more machine-executable instructions for programming a processor in a display system, the display system including a display device, a first display controller, a second display controller and a processor, to perform a method, the method comprising the steps of:

receiving display data, the display data being received at the first display controller from the processor, the first display controller present in the display system;

switching control of the display device between the first display controller and the second display controller, the control of the display device being switched in proximity to a trailing edge of an input vertical synchronization (V-sync) pulse, the second display controller being present in the display system; and

refreshing the display device, the display device being refreshed by the second display controller with a clock independent of the processor and the first display controller.

19. A system, comprising:

a display system, the display system comprising a display device, a first display controller, a second display controller and a processor, the second display controller being optimized for low-power operation;

wherein the display system is configured to perform;

receiving display data from the processor, the display data being received at the first display controller;

switching control of the display device between the first display controller and the second display controller, the control of the display device being switched in proximity to a trailing edge of an input vertical synchronization (V-sync) pulse; and

refreshing the display device, the display device being refreshed by the second display controller with a clock independent of the processor and the first display controller.

20. The system of claim 19, wherein the display system is configured to further perform storing a frame into a frame buffer of the second display controller, the storing of the frame being commenced at the trailing edge of the input V-sync pulse.

21. The system of claim 19, wherein the display system is configured to further perform a transition between one or more video timings of the first display controller and one or more video timings of the second display controller.

22. The system of claim 21, wherein the display system is configured to further perform synchronously re-initializing the one or more video timings of the first display controller and the second display controller, the one or more video timings being synchronously re-initialized during a blanking interval.

23. The system of claim 19, wherein the display system is configured to further perform activating the second display controller from an inactive mode, the second display controller being activated by the processor when the processor receives an input from one or more input devices.

24. The system of claim 19, wherein the display system is configured to further perform commanding the first display controller to activate one or more video outputs when one or more new frames are written to a frame buffer of the first display controller.

25. The system of claim 19, wherein the display system is configured to further perform autonomously driving the display device by the second display controller when no new frame is written to a frame buffer of the first display controller.