SRAM with embedded ROM
First Claim
1. An integrated circuit, comprising:
- a memory cell array including a first memory cell, the first memory cell includes;
first and second pass transistors that include a gate electrode connected to a word line;
a first inverter including;
a first pull-up transistor including a source electrode connected to a first voltage source and a body tie connected to a first well bias voltage, andan output of the first inverter is coupled to a first complementary bit line via the first pass transistor; and
a second inverter including;
a first pull-up transistor including a source electrode connected to the first voltage source and a body tie connected to a second well bias voltage, the first well bias voltage is greater than the second well bias voltage when a Read-Only Memory (ROM) enable signal is set to a first state, andan output of the second inverter is coupled to a first true bit line via the second pass transistor.
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Accused Products
Abstract
An integrated circuit includes first and second memory cells including a first pull-up transistor each having a body tie coupled to respective first and second well bias voltages. Drain electrodes of the first and second pull-up transistors are coupled to a first true bit line and a first complementary bit line, respectively. A second memory cell includes first and second pull-up transistors each having a body tie coupled to the second and first well bias voltages, respectively. Drain electrodes of the first and second pull-up transistors are coupled to a second true bit line and a second complementary bit line, respectively. The first well bias voltage is lower than the second well bias voltage during a Read-Only Memory (ROM) mode, and the first well bias voltage is the same as the second well bias voltage during a Static Random Access Memory (SRAM) mode.
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Citations
20 Claims
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1. An integrated circuit, comprising:
a memory cell array including a first memory cell, the first memory cell includes; first and second pass transistors that include a gate electrode connected to a word line; a first inverter including; a first pull-up transistor including a source electrode connected to a first voltage source and a body tie connected to a first well bias voltage, and an output of the first inverter is coupled to a first complementary bit line via the first pass transistor; and a second inverter including; a first pull-up transistor including a source electrode connected to the first voltage source and a body tie connected to a second well bias voltage, the first well bias voltage is greater than the second well bias voltage when a Read-Only Memory (ROM) enable signal is set to a first state, and an output of the second inverter is coupled to a first true bit line via the second pass transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An integrated circuit, comprising:
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a first memory cell including a first pull-up transistor having a body tie coupled to a first well bias voltage and a drain electrode coupled to a first true bit line, and a second pull-up transistor having a body tie coupled to a second well bias voltage and a drain electrode coupled to a first complementary bit line; a second memory cell including a first pull-up transistor having a body tie coupled to the second well bias voltage, a second pull-up transistor with a body tie coupled to the first well bias voltage, a drain electrode of the first pull-up transistor is coupled to a second true bit line and a drain electrode of the second pull-up transistor is coupled to a second complementary bit line; the first well bias voltage is lower than the second well bias voltage during a Read-Only Memory (ROM) mode; and the first well bias voltage is the same as the second well bias voltage during a Static Random Access Memory (SRAM) mode. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A method comprising:
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forming a first memory cell in an integrated circuit, the first memory cell including a first pull-up transistor having a body tie coupled to a first well bias voltage, a second pull-up transistor with a body tie coupled to a second well bias voltage, a first pass transistor including a gate electrode coupled to a word line, a second pass transistor including a gate electrode coupled to the word line, a drain electrode of the first pull-up transistor is coupled to a first true bit line and a drain electrode of the second pull-up transistor is coupled to a first complementary bit line; forming a second memory cell in the integrated circuit, the second memory cell including a first pull-up transistor having a body tie coupled to the second well bias voltage, a second pull-up transistor with a body tie coupled to the first well bias voltage, a first pass transistor including a gate electrode coupled to the word line, a second pass transistor including a gate electrode coupled to the word line, a drain electrode of the first pull-up transistor is coupled to a second true bit line and a drain electrode of the second pull-up transistor is coupled to a second complementary bit line; forming a memory controller coupled to the first and second memory cells in the integrated circuit, the memory controller is operable to control the first well bias voltage to be lower than the second well bias voltage during a Read-Only Memory (ROM) mode, and to control the first well bias voltage to be the same as the second well bias voltage during a Static Random Access Memory (SRAM) mode. - View Dependent Claims (19, 20)
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Specification