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SRAM with embedded ROM

  • US 8,995,178 B1
  • Filed: 10/31/2013
  • Issued: 03/31/2015
  • Est. Priority Date: 10/31/2013
  • Status: Active Grant
First Claim
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1. An integrated circuit, comprising:

  • a memory cell array including a first memory cell, the first memory cell includes;

    first and second pass transistors that include a gate electrode connected to a word line;

    a first inverter including;

    a first pull-up transistor including a source electrode connected to a first voltage source and a body tie connected to a first well bias voltage, andan output of the first inverter is coupled to a first complementary bit line via the first pass transistor; and

    a second inverter including;

    a first pull-up transistor including a source electrode connected to the first voltage source and a body tie connected to a second well bias voltage, the first well bias voltage is greater than the second well bias voltage when a Read-Only Memory (ROM) enable signal is set to a first state, andan output of the second inverter is coupled to a first true bit line via the second pass transistor.

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