Semiconductor memory device
First Claim
1. A semiconductor memory device comprising:
- a plurality of first memory units each comprising a first transistor, first to nth memory cell transistors (n being a natural number), and a second transistor which are serially coupled between a first end and a second end;
a plurality of first lines coupled to the first transistors;
a plurality of second lines coupled to the second transistors;
a bit line coupled to first ends of the first memory units;
a row decoder coupled to the first lines and the second lines;
a first driver configured to output voltage to a selected one of the first lines;
a second driver configured to output voltage to unselected of the first lines;
a third driver configured to output voltage to a selected one of the second lines;
a fourth driver configured to output voltage to unselected of the second lines;
a selector coupled to the row decoder, the selector being configured toselectively individually couple the first line of each of the first memory units to the first or second driver, andselectively individually couple the second line of each of the first memory units to the third or fourth driver.
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Abstract
According to one embodiment, a semiconductor memory device includes memory units each includes a first transistor, memory cell transistors, and a second transistor serially coupled between first and second ends. A memory cell transistor of each memory unit has its gate electrode coupled to each other. A bit line is coupled to the first ends. First and second drivers output voltage applied to selected and unselected first transistors, respectively. Third and fourth drivers output voltage applied to selected and unselected second transistors, respectively. A selector couples the gate electrode of the first transistor of each memory unit to the first or second driver, and that of the second transistor of each memory unit to the third or fourth driver.
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Citations
11 Claims
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1. A semiconductor memory device comprising:
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a plurality of first memory units each comprising a first transistor, first to nth memory cell transistors (n being a natural number), and a second transistor which are serially coupled between a first end and a second end; a plurality of first lines coupled to the first transistors; a plurality of second lines coupled to the second transistors; a bit line coupled to first ends of the first memory units; a row decoder coupled to the first lines and the second lines; a first driver configured to output voltage to a selected one of the first lines; a second driver configured to output voltage to unselected of the first lines; a third driver configured to output voltage to a selected one of the second lines; a fourth driver configured to output voltage to unselected of the second lines; a selector coupled to the row decoder, the selector being configured to selectively individually couple the first line of each of the first memory units to the first or second driver, and selectively individually couple the second line of each of the first memory units to the third or fourth driver. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification