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Semiconductor memory device

  • US 8,995,185 B2
  • Filed: 09/05/2012
  • Issued: 03/31/2015
  • Est. Priority Date: 03/22/2012
  • Status: Active Grant
First Claim
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1. A semiconductor memory device comprising:

  • a plurality of first memory units each comprising a first transistor, first to nth memory cell transistors (n being a natural number), and a second transistor which are serially coupled between a first end and a second end;

    a plurality of first lines coupled to the first transistors;

    a plurality of second lines coupled to the second transistors;

    a bit line coupled to first ends of the first memory units;

    a row decoder coupled to the first lines and the second lines;

    a first driver configured to output voltage to a selected one of the first lines;

    a second driver configured to output voltage to unselected of the first lines;

    a third driver configured to output voltage to a selected one of the second lines;

    a fourth driver configured to output voltage to unselected of the second lines;

    a selector coupled to the row decoder, the selector being configured toselectively individually couple the first line of each of the first memory units to the first or second driver, andselectively individually couple the second line of each of the first memory units to the third or fourth driver.

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